Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)最新文献_第7页

S-parameter models for transient simulation in Verilog-A Verilog-A中瞬态仿真的s参数模型

Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603161

T. Maier, D. Droste, Michael Siegel

引用次数: 2

A low-power sensor interface circuit for remotely powered implants 一种用于远程供电植入物的低功耗传感器接口电路

Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603173

Xiao Liu, C. Dehollain

引用次数: 0

Monolithic power management front end with high voltage dense energy storage for wireless powering 单片电源管理前端，具有高电压密集能量存储，用于无线供电

Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603171

H. Meyvaert, M. Steyaert, Arne Crouwels, Stijn Indevuyst

引用次数: 2

Investigation of two-point modulation to increase the GFSK data rate of PLL-based wireless transceivers of wireless sensor nodes 提高无线传感器节点锁相环无线收发器GFSK数据速率的两点调制研究

Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603109

Hartwig Unterassinger, W. Pribyl, Martin Flatscher, Tony Gschier

引用次数: 0

Modeling of an electrostatically actuated microelectromechanical (MEMS) speaker system 静电驱动微机电(MEMS)扬声器系统建模

Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603181

D. Tumpold, M. Kaltenbacher, C. Glacer, A. Dehé, M. Nawaz

{"title":"Modeling of an electrostatically actuated microelectromechanical (MEMS) speaker system","authors":"D. Tumpold, M. Kaltenbacher, C. Glacer, A. Dehé, M. Nawaz","doi":"10.1109/PRIME.2013.6603181","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603181","url":null,"abstract":"The market for tablets, laptops and mobile devices is increasing rapidly. Device housings get thinner and energy efficiency plays a major role for battery-powered devices. Microelectromechanical (MEMS) loudspeakers, fabricated in complementary metal oxide semiconductor (CMOS) compatible technology merge energy efficient driving technology with cost economical fabrication processes. Fabricating these devices is a elaborating and expensively task. Therefore, the need of computer models, capable of precisely simulating the multi-field interactions is strongly increasing. We use a system of coupled partial differential equations (PDEs) describing the interaction between the electrostatic, mechanical and acoustical field and apply finite element method FEM to solve them. Additionally, we fully take nonlinear effects like large deformations or stress stiffening effects into account. Mortar FEM is used, to efficiently handle the coupling between mechanical and acoustical field. In combination with special boundary conditions, like perfectly matched layers (PML) truncated propagation regions can be applied in the model. We will present simulations of a MEMS speaker system based on a single sided driving mechanism starting at the electric potential applied on the two electrodes and resulting in the generated sound pressure level (SPL).","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134115193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Dynamic Programming based grouping method for RO-PUFs 基于动态规划的ro - puf分组方法

Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603178

Giray Komurcu, A. E. Pusane, G. Dundar

引用次数: 15

Phase Noise comparative analysis of LC oscillators in 28-nm CMOS through the Impulse Sensitivity Function 利用脉冲灵敏度函数对比分析28纳米CMOS中LC振荡器的相位噪声

Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603102

Ilias Chlis, D. Pepe, D. Zito

引用次数: 10

An automatic calibration circuit for 12-bits single-ramp A-to-D converter in LHC environments LHC环境下12位单斜坡a - d转换器的自动校准电路

Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603108

T. Vergine, M. De Matteis, L. Rota, A. Marchioro, A. Baschirotto

{"title":"An automatic calibration circuit for 12-bits single-ramp A-to-D converter in LHC environments","authors":"T. Vergine, M. De Matteis, L. Rota, A. Marchioro, A. Baschirotto","doi":"10.1109/PRIME.2013.6603108","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603108","url":null,"abstract":"A calibration circuit for single-ramp A-to-D converters is presented here. The calibration circuit allows to automatically compensate the process/mismatch and radiation effects on the A-to-D converter, improving performance and Equivalent Number of Bits. In particular, the calibration circuit is able to automatically align the ramp signal reference used for the conversion in single slope architectures A-to-D architectures, compensating slope deviations due to technological/electrical reasons. Moreover, the calibration circuit shares the same analog circuits of the A-to-D converter, requiring only a small additional power budget and logic for the implementation. The calibration circuit has been validated, testing the overall A-to-D converter after the calibration. A 12 steps binary search is required to calibrate the A-to-D converter (about 2.5ms). This calibration circuit is able to guarantee an 11bits accuracy, in the worst case simulation corner. The technology used is a 65 nm CMOS. The clock frequency has been set to 20 MHz and the power consumption is about 400 μW.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124991011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Monte Carlo based post-silicon verification considering automotive application variances 考虑汽车应用差异的蒙特卡罗后硅验证

Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603132

Manuel Harrant, T. Nirmaier, Jérôme Kirscher, C. Grimm, G. Pelz

引用次数: 3

Conquering variability in mixed-signal ICs 克服混合信号集成电路的可变性

Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603143

C. Wegener, H. M. von Staudt

{"title":"Conquering variability in mixed-signal ICs","authors":"C. Wegener, H. M. von Staudt","doi":"10.1109/PRIME.2013.6603143","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603143","url":null,"abstract":"Summary form only given: Shrinking feature sizes in IC manufacturing are required for implementing Moore's law of doubling device density. Higher device density enables increasing digital IC performance. For mixed-signal ICs, shrinking transistor size implies increasing variability of analog device parameters. This has prevented analog circuit designs to benefit from shrinking process geometries. At the same time, increasing (digital) performance causes increasing customer expectations also regarding analog performance parameters. Conquering the effects of increased variability is an engineering challenge. Trimming and calibration is a design solution to this challenge. However, the cost incurred during IC manufacturing can become a significant part of the overall product cost, especially, when trimming is performed as part of product test. Design-for-Test (DfT) is a key for reducing the cost of product test by providing test access mechanisms and built-in self-tests. Extending DfT to Design-for-Trimming and Calibration is part of Dialog Semiconductor's approach to design challenges for the next generation ICs. In this contribution, we show-case examples of bridging between design and test for the implementation of mixed-signal ICs used in mobile communication platforms.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125056314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1