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Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)最新文献

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Technique for reducing on-resistance of high-voltage drivers based on stacked standard CMOS 基于堆叠标准CMOS的降低高压驱动器导通电阻技术
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603145
Sara Pashmineh, Hongcheng Xu, D. Killat
{"title":"Technique for reducing on-resistance of high-voltage drivers based on stacked standard CMOS","authors":"Sara Pashmineh, Hongcheng Xu, D. Killat","doi":"10.1109/PRIME.2013.6603145","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603145","url":null,"abstract":"This paper presents a new technique for reducing on-resistance of high-voltage drivers, which are based on N-stacked standard CMOS. A theory to calculate gate voltages of HV-driver transistors to drive the maximum drain current for minimum on-resistance is introduced. According to the calculated gate voltages, a circuit design methodology for generating them is described. This concept is technology independent and compatible with scaled CMOS devices. The theory and circuit design are proved by simulating a 2-stack CMOS driver in 65-nm technology, demonstrating significantly improved rise and fall times of the driver, if compared to previous work.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115472784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
FPGA based silicon innovation exploiting “More than Moore” technology 基于FPGA的硅创新利用“超越摩尔”技术
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603140
P. Quinn
{"title":"FPGA based silicon innovation exploiting “More than Moore” technology","authors":"P. Quinn","doi":"10.1109/PRIME.2013.6603140","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603140","url":null,"abstract":"The most recent series of Xilinx FPGAs in 28nm host a wide range of the most advanced technologies. 3D-IC technology has allowed for a doubling of logic capacity in a single device, commensurate with going to the next process node, with the added advantages of reduced power and improved yield. New levels of programmable systems integration are enabled through the cointegration of digital FPGA die with dedicated analog die such as high-speed analog SerDes on a single interposer. Such heterogeneous integration delivers an industry leading 2.8Tb/s of off-chip serial connectivity. This talk reviews what's driving Moore scaling and how it impacts FPGA technology scaling relative to ASSPs and ASICs. It goes on to cover such items as process selection, 3D-IC technology, analog features, as well as power reduction strategies and the migration steps to 20nm and 16nm.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123805921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analog design trends in communication systems 通信系统中的模拟设计趋势
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603137
J. Hauptmann, Dario Giotta, Ulrich Gaier
{"title":"Analog design trends in communication systems","authors":"J. Hauptmann, Dario Giotta, Ulrich Gaier","doi":"10.1109/PRIME.2013.6603137","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603137","url":null,"abstract":"Modern high-speed silicon technologies in the submicron region enable today very efficient and cost effective digital communication systems. Highly integrated system-on-chip (SoC) solutions cover satisfying the ever-increasing demand for broadband communication from home. High data transfer rates with excellent quality are achieved through the use of Wi-Fi, DSL, Ethernet and optical transport. The presentation will deal with the most important design aspects and system trends that occur in the development of RF- and MS-front-end modules for SoC integration. New trends in wireless, as well as requirements for individual MS/RF blocks are considered with respect to high integration and cost reduction.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124236790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimal deployment of shadowed registers in systems with serial clock distribution 具有串行时钟分布的系统中阴影寄存器的最佳部署
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603123
Mario Trifkovic, D. Raic, D. Strle
{"title":"Optimal deployment of shadowed registers in systems with serial clock distribution","authors":"Mario Trifkovic, D. Raic, D. Strle","doi":"10.1109/PRIME.2013.6603123","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603123","url":null,"abstract":"Digital sections in several high-precision mixed systems operate at a relatively low frequency, allowing the trading of speed for the mitigation of switching noise and power distribution problems. While the serial clock distribution potentially solves most of these problems, the standard library cells and synthesis tools do not provide much, if any support for the serial clock tree implementation. In our work we propose the necessary design flow modification and seek the optimal clock signal allocation for the deployment of shadowed registers subject to timing constraints and minimal area overhead.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"203 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121160901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An analog 1:16 demultiplexer for time-interleaved A/D-converters with a sampling rate of up to 64 GS/s 模拟1:16解复用器，用于时间交错A/ d转换器，采样率高达64gs /s
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603150
F. Lang, Janina Gerigk, D. Ferenci, M. Grozing, M. Berroth
{"title":"An analog 1:16 demultiplexer for time-interleaved A/D-converters with a sampling rate of up to 64 GS/s","authors":"F. Lang, Janina Gerigk, D. Ferenci, M. Grozing, M. Berroth","doi":"10.1109/PRIME.2013.6603150","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603150","url":null,"abstract":"An analog current-based 1:16-demultiplexer with integrated sample-and-hold is presented. It is designed in a 28 nm CMOS technology and is the basis for a 16-fold time-interleaved ADC. It offers sampling rates up to 64 GS/s, while consuming only 0.9 W of power and 2.6 mm2 of chip area.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127969394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Graph Coverage: An FPGA-targeted implementation 图形覆盖:针对fpga的实现
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603103
Alessandro Cinti, A. Rizzi
{"title":"Graph Coverage: An FPGA-targeted implementation","authors":"Alessandro Cinti, A. Rizzi","doi":"10.1109/PRIME.2013.6603103","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603103","url":null,"abstract":"Classification systems specifically designed to deal with fully labeled graphs are gaining importance in many application fields. The main computational bottleneck in such systems is the dissimilarity measure between pairs of graphs. In this paper we propose to accelerate in hardware such computations, relying on the Graph Coverage as the core inexact graph matching procedure, targeting the design to FPGA as an inexpensive way to design specific co-processing devices. A comparison in terms of computational time between the proposed system and a software implementation on a standard workstation shows encouraging results.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130293138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Extended model for platinum diffusion in silicon 铂在硅中的扩散扩展模型
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603162
Elie Badr, P. Pichler, G. Schmidt
{"title":"Extended model for platinum diffusion in silicon","authors":"Elie Badr, P. Pichler, G. Schmidt","doi":"10.1109/PRIME.2013.6603162","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603162","url":null,"abstract":"Close to the wafer surfaces, our platinum diffusion experiments were found to be at gross discrepancy with the predictions of well-established diffusion models. These differences are associated with the ramping-down of the temperature at the end of the diffusion processes. To obtain a consistent model able to explain the experiments reported previously in the literature together with our experiments, energy barriers had to be included for the various reactions rate. For the Frank-Turnbull, kick-out and bulk recombination reactions, barrier heights of 0.55, 0.16, and 0.57 eV were determined, respectively. The newly established model is able to reproduce platinum diffusion for a considerably wider range of experimental conditions than models before.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132680415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Novel field programmable embryonic cell for adder and multiplier 用于加法器和乘法器的新型野外可编程胚胎细胞
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603121
Gayatri Malhotra, J. Becker, M. Ortmanns
{"title":"Novel field programmable embryonic cell for adder and multiplier","authors":"Gayatri Malhotra, J. Becker, M. Ortmanns","doi":"10.1109/PRIME.2013.6603121","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603121","url":null,"abstract":"A novel approach for the implementation of a field programmable embryonic cell is proposed. This is inspired from the concept of cloning used by biological cells to grow a bigger organism. An exemplary full adder and multiplier circuit evolution is simulated using Verilog and verified. An automated generation of configuration data for the embryonic cells from a behavioral description of the overall organism can be done using a genetic algorithm approach in the future.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133744982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Off-line BIST in watt hour meters 离线电能表BIST
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603120
Rok Ribnikar, D. Strle
{"title":"Off-line BIST in watt hour meters","authors":"Rok Ribnikar, D. Strle","doi":"10.1109/PRIME.2013.6603120","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603120","url":null,"abstract":"In this work the concept, circuits and algorithms for an efficient off-line Built-In Self-Test (BIST) in watt hour meters are presented. On-chip signal generator is needed and additional digital hardware is necessary to evaluate the result. For a good signal to noise ratio (SNR) as well as good frequency resolution, a large number of samples would be needed to accurately calculate the FFT of the result. This approach is time-consuming and inappropriate for BIST, since it requires too much silicon area. We tried to avoid FFT calculation and replace it with small digital hardware and hardware algorithm running on the chip. The most important errors, which may happen in measurement path during the operation of the watt hour meter, can be efficiently detected. The parameters obtained by the suggested BIST hardware/algorithm were compared to the results obtained by the FFT for verification. The results confirm that the proposed concept of BIST could be used for an efficient on chip and off-line built-in self-test.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115046280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Zoom FFT for precise spectrum calculation in FMCW radar using FPGA 利用FPGA实现FMCW雷达精确频谱计算的缩放FFT
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603180
B. Al-Qudsi, N. Joram, A. Strobel, F. Ellinger
{"title":"Zoom FFT for precise spectrum calculation in FMCW radar using FPGA","authors":"B. Al-Qudsi, N. Joram, A. Strobel, F. Ellinger","doi":"10.1109/PRIME.2013.6603180","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603180","url":null,"abstract":"The zoom FFT (ZFFT) has been utilized in various digital signal processing systems, it is used when a fine spectral resolution is needed within a small portion of a signal's overall frequency range. It has been implemented in different fields and for different applications. This paper presents an implementation method of the ZFFT approach to estimate the spectral peak in the FMCW radar using a field programmable gate arrays (FPGA). It has been utilized to decrease the calculations complexity, hence, reduction the power consumption. The approach has been realized and a complexity reduction factor of up to 8 has been gained and tested on an FMCW radar processing system.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124040775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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