Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)最新文献

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Integrated Class-D audio amplifier virtual test for output EMI filter performance 集成d类音频放大器输出EMI滤波性能虚拟测试
R. Mrad, F. Morel, G. Pillonnet, C. Vollaire, A. Nagari
{"title":"Integrated Class-D audio amplifier virtual test for output EMI filter performance","authors":"R. Mrad, F. Morel, G. Pillonnet, C. Vollaire, A. Nagari","doi":"10.1109/PRIME.2013.6603127","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603127","url":null,"abstract":"This paper proposes a model based on the segmentation technique that can be used for electromagnetic interference (EMI) filter test by simulation. It is dedicated for systems with a differential output. The present approach proposes virtual measurement of the filter performance in the final application. Thus, the source emissions and the load impedance are taken into account. The proposed approach uses impedance matrices to model the passive parts of the system. A matrix calculation permits to associate these matrices and create a compact model. The impedance matrices and the converter output voltages are used for currents and voltages computation at all the system points. Finally, the proposed method is applied and validated on a Class-D amplification system. This method shows good accuracy on the [1kHz-120MHz] frequency band.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131394667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A SiGe LTE power amplifier with capacitive tuning for size-reduction of biasing inductor 一种用于减小偏置电感尺寸的电容调谐SiGe LTE功率放大器
Jinshu Zhao, R. Wolf, F. Ellinger
{"title":"A SiGe LTE power amplifier with capacitive tuning for size-reduction of biasing inductor","authors":"Jinshu Zhao, R. Wolf, F. Ellinger","doi":"10.1109/PRIME.2013.6603168","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603168","url":null,"abstract":"This paper demonstrates a fully integrated power amplifier for long term evolution (LTE) applications. The power amplifier is adopting a tuning capacitor in parallel with the choke inductor, which reduces the DC power consumption of the inductor and decreases the chip size. The total power added efficiency (PAE) is enhanced as a result. The proposed power amplifier is manufactured using a 0.25 μm SiGe hetero-junction bipolar transistor (HBT) process. For a LTE signal with a centre frequency of 2.1 GHz, the PA delivers an output power of 21.3 dBm with the power added efficiency (PAE) of 21% and power gain of 19.5 dB at the 1 dB compression point. For the LTE downlink quadrature amplitude modulation (QAM64) signal at 2.11 GHz with 20 MHz channel bandwidth, the measured ACLR is below -30 dBc for the output power of 18 dBm with PAE above 15%. The error vector magnitude (EVM) specifications are met for LTE 20 MHz bandwidth QPSK modulation scheme, and complied with 1 dB power back-off for QAM16 signal and at 2 dB power back-off for QAM64 modulation scheme. The measurement results verify that the proposed method is promising for the application of the fully integrated PA.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121451155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Infineon technologies: From product to system and the human resources excellence as key competitive advantage 英飞凌科技:将从产品到系统以及卓越的人力资源作为关键竞争优势
S. Herlitschka
{"title":"Infineon technologies: From product to system and the human resources excellence as key competitive advantage","authors":"S. Herlitschka","doi":"10.1109/PRIME.2013.6603136","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603136","url":null,"abstract":"Summary form only given. Major global challenges of the 21st century are drivers for the industry and especially for the semiconductor industry. Microelectronics and semiconductors are key enabling technologies and will contribute significantly to increasing Innovation and Productivity. Infineon provides semiconductors and system solutions, focusing on three central needs of modern society: Energy Efficiency, Mobility and Security. Tight Customer Relationships are based on system know-how and application understanding. People in our company are the key to our success. Their experiences, knowledge and passion drive us to new levels of excellence. Thus, people excellence is a core element of our strategy. Our success depends on creating an attractive and stimulating working environment for our employees, who represent \"living\" diversity with staff coming from 55 nations. As one of the most innovative companies, Infineon has set up a corporate PhD network. For our PhD's we offer best conditions for up-to-date research & development and an attractive multi-disciplinary educational opportunity at an international workplace. The presentation will provide an overview on current technology developments in Infineon's focus areas and PhDs' opportunities to become part of a successful global company.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122125417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Power-aware architectural exploration of the CORDIC algorithm CORDIC算法的功耗感知架构探索
Jennifer Manica, R. Passerone, Luca Rizzon
{"title":"Power-aware architectural exploration of the CORDIC algorithm","authors":"Jennifer Manica, R. Passerone, Luca Rizzon","doi":"10.1109/PRIME.2013.6603179","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603179","url":null,"abstract":"Mobile applications require the use of specialized design techniques to reduce power consumption and maximize battery life. New implementation technologies are able to reduce energy at the device level. At the same time, architectural choices can lead to significantly different power consumption profiles for equivalent implementations of the same function. In this paper we focus on the architectural level, and analyze various implementation alternatives for the CORDIC function. Our results provide insight into the trade-offs between area, performance and power consumption, and give designers directions for their architectural choices.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130418723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A continuous time switched capacitor DAC with offset and flicker noise cancellation 具有偏移和闪烁噪声消除的连续时间开关电容DAC
A. N. Longhitano, F. del Cesta, P. Bruschi, R. Simmarano
{"title":"A continuous time switched capacitor DAC with offset and flicker noise cancellation","authors":"A. N. Longhitano, F. del Cesta, P. Bruschi, R. Simmarano","doi":"10.1109/PRIME.2013.6603151","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603151","url":null,"abstract":"A switched capacitor DAC, capable of producing a continuous time output signal, is presented. The multiphase conversion cycle allows cancellation of the input offset and low frequency noise of both op-amps used in the circuit. Electrical simulations, performed on a 12 bit prototype, designed by means of UMC 0.18 um MM/RF CMOS process, are shown. The main estimated performances are: 2.4 us conversion time, 0.42 mW power consumption at 1.8 V power supply, 0.49 mV rms output noise over a 400 kHz bandwidth.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125495212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Cascode class-E power amplifier in 180/350 nm CMOS for EER system 用于EER系统的180/350 nm CMOS级e级功率放大器
I. Rumyancev, A. Korotkov, J. Hauer
{"title":"Cascode class-E power amplifier in 180/350 nm CMOS for EER system","authors":"I. Rumyancev, A. Korotkov, J. Hauer","doi":"10.1109/PRIME.2013.6603167","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603167","url":null,"abstract":"Cascode class-E power amplifier in 180/350 nm CMOS for envelope elimination and restoration system is presented. Designed amplifier achieves 21 dBm output power and 44% PAE at 1900 MHz with 3 V supply voltage. Charging acceleration technique is used for efficiency enhancement. ESD protection problem is discussed.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126782966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Fast constant time memory allocator for inter task communication in ultra low energy embedded systems 用于超低功耗嵌入式系统任务间通信的快速恒时内存分配器
G. Rebel, F. Estévez, Ingo Schulz, P. Glosekotter
{"title":"Fast constant time memory allocator for inter task communication in ultra low energy embedded systems","authors":"G. Rebel, F. Estévez, Ingo Schulz, P. Glosekotter","doi":"10.1109/PRIME.2013.6603114","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603114","url":null,"abstract":"Modern microcontrollers provide enough processing power to benefit from the advantages of multitasking schedulers or operating systems even in the area of small, battery based or energy self-sustaining devices. Many of these devices communicate with other devices via different interfaces. For a multitasking operating system, communication means to collect individual bytes in memory blocks and to transport these blocks between tasks. This paper describes how to use a combination of memory pools and memory headers to provide a fast, constant time memory allocator with low internal fragmentation. The proposed memory allocator is fast enough and has so few internal fragmentation, that it is applicable even in ultra low energy embedded systems with few kilobytes of ram. It can provide memory blocks of equal size at high frequency.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126987772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An improved ultra-low-power wireless sensor-station supplied by a photovoltaic harvester 一种改进的超低功耗无线传感器站,由光伏收集器提供
A. L. Barnabei, E. Dallago, P. Malcovati, A. Liberale
{"title":"An improved ultra-low-power wireless sensor-station supplied by a photovoltaic harvester","authors":"A. L. Barnabei, E. Dallago, P. Malcovati, A. Liberale","doi":"10.1109/PRIME.2013.6603155","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603155","url":null,"abstract":"In this work we describe a system optimized to use the few microwatts generated by a 4 mm2 photovoltaic energy harvester to acquire, process and wirelessly transmit information about the environment temperature and light irradiance. The energy needed for the described power-expensive operations is obtained by charging a buffer capacitor while the system is in a low-power-consumption state. A voltage level detector senses the charging status of the capacitor and wakes-up the sensing station every time enough energy is stored. Thus, the environmental parameters are monitorized and transmitted with an asynchronous and intermittent strategy. The optimization work related to this paper has persued the target of minimize the unerasable continuous power consumption of the voltage detector during the charging of the capacitor. We reached the goal of reducing it from the 50 μW of the previous version of the system to the current 5 μW, with a significant usability improvement. Simulations and experimental evidences demonstrate that our station can work totally battery-free when just illuminated with 100 W/m2 of light irradiance, transmitting data with a 802.15.4 compliant protocol and potentially occupies a volume of 1 cm3.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121908430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Design of a reconfigurable multi-core architecture for streaming applications with a case study on performance evaluation of FIR-filters 流媒体应用的可重构多核架构设计,并以fir滤波器性能评估为例
Leyla S. Ghazanfari, Roberto Airoldi, J. Nurmi, T. Ahonen
{"title":"Design of a reconfigurable multi-core architecture for streaming applications with a case study on performance evaluation of FIR-filters","authors":"Leyla S. Ghazanfari, Roberto Airoldi, J. Nurmi, T. Ahonen","doi":"10.1109/PRIME.2013.6603154","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603154","url":null,"abstract":"This paper presents a reconfigurable multi-core architecture which is composed of nine nodes connected to each other in a mesh topology network. The central node hosts a general purpose processor and serves as the system controller and the surrounding nodes are equipped with coarse grain reconfigurable arrays that provide hardware flexibility and parallelism. This architecture is mainly targeted for streaming applications. As a case study, performance and hardware usage for implementations of FIR filters with different number of taps are presented. Each implementation was prototyped on an Altera FPGA and to ensure the correctness of the system, RTL simulations were carried out. The performance results were compared with the same applications implemented on a single-core processor. The timing analyses show speed-ups up to 3.6x.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133866861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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