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Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)最新文献

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Portable battery charging circuits for enhanced magnetic resonance Wireless Power Transfer (WPT) system 增强磁共振无线电力传输(WPT)系统的便携式电池充电电路
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603170
Hyun Jin Choi, Eun Hye Ahn, S. Park, J. Choi
{"title":"Portable battery charging circuits for enhanced magnetic resonance Wireless Power Transfer (WPT) system","authors":"Hyun Jin Choi, Eun Hye Ahn, S. Park, J. Choi","doi":"10.1109/PRIME.2013.6603170","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603170","url":null,"abstract":"In recent years there has been significant development in the field of consumer electronics and biomedical applications based on wireless power transfer technology. In this paper, we propose efficiency improvement method for magnetic resonance Wireless Power Transfer (WPT) at a particular frequency within ISM band, applying controlled Impedance Matching technique. The impedance matching network guides the system to maintain the resonance condition when distance between Transmitter (Tx) and Receiver (Rx) is varied, which results in high power transfer efficiency. Measured results with proposed scheme showed an average of 7.21% improvement in power efficiency for distance between 10cm to 100cm. In addition an on-chip high efficient power recovery scheme is designed and fabricated in Dongbu HiTek's (DBHs) 0.35μm BCD technology based on LOCOS 0.35μm CMOS process for portable battery recharging applications. A maximum overall efficiency be 70.2% was determined for the entire system. This work shows the potential of automatic adjustments of parameters, such as impedance, in order to maintain resonance frequency to attain the maximum power efficiency and also to make the device portable.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"269 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123852017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A low-power, continuous-time sigma-delta modulator for MEMS microphones 用于MEMS传声器的低功耗、连续时间σ - δ调制器
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603116
C. De Berti, P. Malcovati, L. Crespi, A. Baschirotto
{"title":"A low-power, continuous-time sigma-delta modulator for MEMS microphones","authors":"C. De Berti, P. Malcovati, L. Crespi, A. Baschirotto","doi":"10.1109/PRIME.2013.6603116","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603116","url":null,"abstract":"This paper presents a continuous-time ΣΔ ADC for MEMS microphone integrated interface applications. The ΣΔ modulator features a 3rd-order loop filter realized with only two operational amplifiers to reduce power consumption. It exploits a 15-level quantizer and 3-MHz sampling frequency to minimize the impact of clock jitter. The proposed architecture can handle an excess loop delay of half period of the sampling clock. The ΣΔ modulator, simulated at transistor-level, performs a 105.5dB A-weighted dynamic range (DR) and a 100.8 dB signal-to-noise-and-distortion ratio (SNDR) at -2 dBFS. The device operates from a single 1.8 V and consumes 200 μW.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130736068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Fully electrical test procedure for inertial MEMS characterization at wafer-level 晶圆级惯性MEMS特性的全电气测试程序
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603130
A. Sisto, O. Schwarzelbach, L. Fanucci
{"title":"Fully electrical test procedure for inertial MEMS characterization at wafer-level","authors":"A. Sisto, O. Schwarzelbach, L. Fanucci","doi":"10.1109/PRIME.2013.6603130","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603130","url":null,"abstract":"The fast growth of MEMS technologies for the production of inertial sensors in the last decade makes the characterization at wafer-level very important. In this paper is presented a test setup for measuring electrical and mechanical parameters of capacitive MEMS inertial sensors. The test setup is used in the production for automotive and consumer applications. It is fully electrical (i.e. none of the stimuli to the sensors is mechanical). The core of the test setup is a test algorithm. The design of the test algorithm was aimed at a fast, reliable and repeatable wafer-sort test. With the test setup described in this paper, it is possible to measure electrical and mechanical parameters of inertial sensors with up-to-6 dimensions.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"289 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115918058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Design of mixers for a 130-GHz transceiver in 28-nm CMOS 采用28nm CMOS的130 ghz收发器混频器设计
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603100
D. Parveg, M. Varonen, M. Karkkainen, K. Halonen
{"title":"Design of mixers for a 130-GHz transceiver in 28-nm CMOS","authors":"D. Parveg, M. Varonen, M. Karkkainen, K. Halonen","doi":"10.1109/PRIME.2013.6603100","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603100","url":null,"abstract":"A compact and 3-dB bandwidth of 118-145-GHz Gilbert-cell mixer for up-conversion and a 1-dB bandwidth of 106-143-GHz image-rejection (IR) resistive mixer for down-conversion are designed for a 130-GHz transceiver in 28-nm CMOS technology. A wide 10-GHz intermediate frequency (IF) tuning range is obtained for both mixers. The simulated results show a +1.6-dB conversion gain for the Gilbert-cell mixer with a layout size of 720×633 μm2 and 6.1 mW of DC power consumption. An 11-dB conversion loss and 30-dB IR ratio are simulated for the resistive mixer with a layout size of 845×794 μm2. The simulated 1-dB output compression point is -8 dBm for the Gilbert-cell mixer and 1-dB input compression point is +9 dBm for the resistive mixer.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116323193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
tLIFTING: An open-source multi-level fault simulator for ionizing effects tLIFTING:用于电离效应的开源多级故障模拟器
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603133
Feng Lu, G. Di Natale, M. Flottes, B. Rouzeyre
{"title":"tLIFTING: An open-source multi-level fault simulator for ionizing effects","authors":"Feng Lu, G. Di Natale, M. Flottes, B. Rouzeyre","doi":"10.1109/PRIME.2013.6603133","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603133","url":null,"abstract":"This paper presents a multi-level simulator tLIFTING for fault simulation in digital circuits. Multi-level simulation is used for precision of the information of the fine grain transistor level and the conciseness of the coarse grain logic level. This multi-level process allows handling natural and maliciously induced physical phenomenon leading to circuit misbehavior, while dealing with large circuits.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121042065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An improved instruction-level energy model for RISC microprocessors 一种改进的RISC微处理器指令级能量模型
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603186
Wei Wang, Mark Zwolinski
{"title":"An improved instruction-level energy model for RISC microprocessors","authors":"Wei Wang, Mark Zwolinski","doi":"10.1109/PRIME.2013.6603186","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603186","url":null,"abstract":"The power and energy consumed by a chip have become primary design constraints for embedded systems and are largely affected by software. However, there is a gap between software and hardware that makes it hard to predict which code consumes the least power before running it. Therefore, it is vital to discover which factors affect a program's energy consumption. In this paper we present an instruction-level power model for a single core, in-order RISC processor architecture. We do not analyze each instruction individually, but we study the average power and running time instead. We find the power in a processor is nearly constant, no matter what instructions are run, but the IO port power is related to the behavior of the program. Furthermore, we provide a model that takes the cache miss rate into consideration.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"47 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131652491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Circuit simulation using state space equations 利用状态空间方程进行电路仿真
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603135
K. A. Lam, Mark Zwolinski
{"title":"Circuit simulation using state space equations","authors":"K. A. Lam, Mark Zwolinski","doi":"10.1109/PRIME.2013.6603135","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603135","url":null,"abstract":"This paper proposes a method to recast the classic circuit simulation algorithm to maximize parallelism by formulating the circuit equations as state variable equations and using an integration method such as Runge Kutta as the foundation to break the time dependencies. A brief introduction to the SPICE algorithm and previous attempts to exploit parallelism is given. The implementation of the new algorithm for both linear and non-linear circuits is presented and results are compared with the traditional method. The opportunities for extracting parallelism are discussed.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133251784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
CMOS current amplifier for AFM impedance sensing on chip with ZeptoFarad resolution 具有ZeptoFarad分辨率的AFM阻抗传感芯片CMOS电流放大器
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603124
D. Bianchi, M. Carminati, G. Ferrari, M. Sampietro
{"title":"CMOS current amplifier for AFM impedance sensing on chip with ZeptoFarad resolution","authors":"D. Bianchi, M. Carminati, G. Ferrari, M. Sampietro","doi":"10.1109/PRIME.2013.6603124","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603124","url":null,"abstract":"A new sensing configuration based on the direct use of the metal input pad of a dedicated CMOS amplifier as a conductive substrate electrode for nanoscale high-performance electrical measurement with a standard conductive AFM is proposed and experimentally validated. Combining the state-of-the-art performance of an integrated current preamplifier (5MHz bandwidth, 14fA/sqrt(Hz) noise at 1MHz) with pad and setup optimization, it has been possible to straightforwardly achieve 14zF total capacitive rms resolution (0.5V applied at 1MHz with 1s averaging time) that corresponds to 75pm resolution in tracking the piezo vertical movement (allowing the detection of 6nm steps of the cantilever with a SNR of ~40dB).","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134308355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Diode detector with voltage gain 具有电压增益的二极管检测器
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603146
R. Wolf, F. Ellinger
{"title":"Diode detector with voltage gain","authors":"R. Wolf, F. Ellinger","doi":"10.1109/PRIME.2013.6603146","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603146","url":null,"abstract":"We propose a detector with the properties of a diode detector and with additional voltage gain within the same circuit. Thereto, the principle of the diode detector is implemented by an active control loop. By calculations, it is proven that the behavior is similar to the conventional diode detector. This is validated by measurements of a detector circuit which was implemented as part of an integrated circuit for an envelope following system. Additionally, we show by calculations that it is possible to modify the circuit such that it reveals better properties.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131136729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
System-level power optimization for a ΣΔ D/A converter for hearing-aid application 用于助听器应用的ΣΔ D/ a转换器的系统级功率优化
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603117
Peter Pracný, I. Jørgensen, Erik Bruun
{"title":"System-level power optimization for a ΣΔ D/A converter for hearing-aid application","authors":"Peter Pracný, I. Jørgensen, Erik Bruun","doi":"10.1109/PRIME.2013.6603117","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603117","url":null,"abstract":"This paper deals with a system-level optimization of a back-end of audio signal processing chain for hearing-aids, including a sigma-delta modulator digital-to-analog converter (DAC) and a Class D power amplifier. Compared to other state-of-the-art designs dealing with sigma-delta modulator design for audio applications we take the maximum gain of the modulator noise transfer function (NTF) as a design parameter. By increasing the maximum NTF gain the cutoff frequency of modulator loop filter is increased which lowers the in-band quantization noise but also lowers the maximum stable amplitude (MSA). This work presents an optimal compromise between these. Increased maximum NTF gain combined with a multi bit quantizer in the modulator allows lower oversampling ratio (OSR) and results in considerable power savings while the audio quality is kept unchanged. The proposed optimization impacts the entire hearing-aid audio back-end system resulting in less hardware and power consumption in the interpolation filter, in the sigma-delta modulator and reduced switching rate of the Class D output stage.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132762224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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