Formal Methods in System Design最新文献_第4页

Concise outlines for a complex logic: a proof outline checker for TaDA 复杂逻辑的简明大纲:TaDA的证明大纲检查器

4区计算机科学

Formal Methods in System Design Pub Date : 2023-07-31 DOI: 10.1007/s10703-023-00427-w

Felix A. Wolf, Malte Schwerhoff, Peter Müller

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引用次数: 6

Dissecting ltlsynt 剖析ltlsynt

IF 0.8 4区计算机科学

Formal Methods in System Design Pub Date : 2023-07-14 DOI: 10.1007/s10703-022-00407-6

Florian Renkin, Philipp Schlehuber-Caissier, A. Duret-Lutz, Adrien Pommellet

引用次数: 0

Round- and context-bounded control of dynamic pushdown systems 动态下推系统的圆边界和上下文边界控制

IF 0.8 4区计算机科学

Formal Methods in System Design Pub Date : 2023-07-07 DOI: 10.1007/s10703-023-00431-0

B. Bollig, Mathieu Lehaut, N. Sznajder

引用次数: 0

Symbolic encoding of LL(1) parsing and its applications LL（1）解析的符号编码及其应用

IF 0.8 4区计算机科学

Formal Methods in System Design Pub Date : 2023-06-22 DOI: 10.1007/s10703-023-00420-3

Pankaj Kumar Kalita, Dhruv Singal, Palak Agarwal, Saket Jhunjhunwala, Subhajit Roy

引用次数: 2

Runtime verification of real-time event streams using the tool HStriver 使用HStriver工具对实时事件流进行运行时验证

4区计算机科学

Formal Methods in System Design Pub Date : 2023-06-21 DOI: 10.1007/s10703-023-00428-9

Felipe Gorostiaga, César Sánchez

引用次数: 0

Memory access protocols: certified data-race freedom for GPU kernels 内存访问协议:GPU内核的认证数据竞争自由

IF 0.8 4区计算机科学

Formal Methods in System Design Pub Date : 2023-05-26 DOI: 10.1007/s10703-023-00415-0

Tiago Cogumbreiro, J. Lange, Dennis Liew, Hannah Zicarelli

引用次数: 0

Compositional verification of priority systems using sharp bisimulation 使用尖锐双仿真的优先系统的组成验证

IF 0.8 4区计算机科学

Formal Methods in System Design Pub Date : 2023-05-17 DOI: 10.1007/s10703-023-00422-1

Luca Di Stefano, Frédéric Lang

引用次数: 0

Partial bounding for recursive function synthesis 递归函数合成的部分边界

IF 0.8 4区计算机科学

Formal Methods in System Design Pub Date : 2023-05-16 DOI: 10.1007/s10703-023-00417-y

Azadeh Farzan, Victor Nicolet

引用次数: 0

Isla: integrating full-scale ISA semantics and axiomatic concurrency models (extended version) Isla:集成全面ISA语义和公理并发模型(扩展版本)

4区计算机科学

Formal Methods in System Design Pub Date : 2023-05-12 DOI: 10.1007/s10703-023-00409-y

Alasdair Armstrong, Brian Campbell, Ben Simner, Christopher Pulte, Peter Sewell

{"title":"Isla: integrating full-scale ISA semantics and axiomatic concurrency models (extended version)","authors":"Alasdair Armstrong, Brian Campbell, Ben Simner, Christopher Pulte, Peter Sewell","doi":"10.1007/s10703-023-00409-y","DOIUrl":"https://doi.org/10.1007/s10703-023-00409-y","url":null,"abstract":"Abstract Architecture specifications such as Armv8-A and RISC-V are the ultimate foundation for software verification and the correctness criteria for hardware verification. They should define the allowed sequential and relaxed-memory concurrency behaviour of programs, but hitherto there has been no integration of full-scale instruction-set architecture (ISA) semantics with axiomatic concurrency models, either in mathematics or in tools. These ISA semantics can be surprisingly large and intricate, e.g. 100k $$+$$ <mml:math xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"> <mml:mo>+</mml:mo> </mml:math> lines for Armv8-A. In this paper we present a tool, Isla, for computing the allowed behaviours of concurrent litmus tests with respect to full-scale ISA definitions, in the Sail language, and arbitrary axiomatic relaxed-memory concurrency models, in the Cat language. It is based on a generic symbolic engine for Sail ISA specifications. We equip the tool with a web interface to make it widely accessible, and illustrate and evaluate it for Armv8-A and RISC-V. The symbolic execution engine is valuable also for other verification tasks: it has been used in automated ISA test generation for the Arm Morello prototype architecture, extending Armv8-A with CHERI capabilities, and for Iris program-logic reasoning about binary code above the Armv8-A and RISC-V ISA specifications. By using full-scale and authoritative ISA semantics, Isla lets one evaluate litmus tests using arbitrary user instructions with high confidence. Moreover, because these ISA specifications give detailed and validated definitions of the sequential aspects of systems functionality, as used by hypervisors and operating systems, e.g. instruction fetch, exceptions, and address translation, our tool provides a basis for developing concurrency semantics for these. We demonstrate this for the Armv8-A instruction-fetch and virtual-memory models and examples of Simner et al.","PeriodicalId":12430,"journal":{"name":"Formal Methods in System Design","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135337992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The probabilistic termination tool amber 概率终止工具琥珀

4区计算机科学

Formal Methods in System Design Pub Date : 2023-05-10 DOI: 10.1007/s10703-023-00424-z

Marcel Moosbrugger, Ezio Bartocci, Joost-Pieter Katoen, Laura Kovács

引用次数: 4