{"title":"Automated repair by example for firewalls","authors":"William T. Hallahan, Ennan Zhai, R. Piskac","doi":"10.1007/s10703-020-00346-0","DOIUrl":"https://doi.org/10.1007/s10703-020-00346-0","url":null,"abstract":"","PeriodicalId":12430,"journal":{"name":"Formal Methods in System Design","volume":"56 1","pages":"127 - 153"},"PeriodicalIF":0.8,"publicationDate":"2020-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10703-020-00346-0","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44061970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Paul Gainer, Sven Linker, Clare Dixon, U. Hustadt, M. Fisher
{"title":"Multi-scale verification of distributed synchronisation","authors":"Paul Gainer, Sven Linker, Clare Dixon, U. Hustadt, M. Fisher","doi":"10.1007/s10703-020-00347-z","DOIUrl":"https://doi.org/10.1007/s10703-020-00347-z","url":null,"abstract":"","PeriodicalId":12430,"journal":{"name":"Formal Methods in System Design","volume":"55 1","pages":"171 - 221"},"PeriodicalIF":0.8,"publicationDate":"2020-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10703-020-00347-z","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"52227498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Kwiatkowska, G. Norman, D. Parker, Gabriel Santos
{"title":"Automatic verification of concurrent stochastic systems","authors":"M. Kwiatkowska, G. Norman, D. Parker, Gabriel Santos","doi":"10.1007/s10703-020-00356-y","DOIUrl":"https://doi.org/10.1007/s10703-020-00356-y","url":null,"abstract":"","PeriodicalId":12430,"journal":{"name":"Formal Methods in System Design","volume":"58 1","pages":"188 - 250"},"PeriodicalIF":0.8,"publicationDate":"2020-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10703-020-00356-y","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47698151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Umang Mathur, Matthew S. Bauer, Rohit Chadha, A. Sistla, Mahesh Viswanathan
{"title":"Exact quantitative probabilistic model checking through rational search","authors":"Umang Mathur, Matthew S. Bauer, Rohit Chadha, A. Sistla, Mahesh Viswanathan","doi":"10.1007/s10703-020-00348-y","DOIUrl":"https://doi.org/10.1007/s10703-020-00348-y","url":null,"abstract":"","PeriodicalId":12430,"journal":{"name":"Formal Methods in System Design","volume":"56 1","pages":"90 - 126"},"PeriodicalIF":0.8,"publicationDate":"2020-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10703-020-00348-y","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41579556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Prantik Chatterjee, Subhajit Roy, Bui Phi Diep, A. Lal
{"title":"Distributed bounded model checking","authors":"Prantik Chatterjee, Subhajit Roy, Bui Phi Diep, A. Lal","doi":"10.34727/2020/isbn.978-3-85448-042-6_11","DOIUrl":"https://doi.org/10.34727/2020/isbn.978-3-85448-042-6_11","url":null,"abstract":"Program verification is a resource-hungry task. This paper looks at the problem of parallelizing SMT-based automated program verification, specifically bounded model-checking, so that it can be distributed and executed on a cluster of machines. We present an algorithm that dynamically unfolds the call graph of the program and frequently splits it to create sub-tasks that can be solved in parallel. The algorithm is adaptive, controlling the splitting rate according to available resources, and also leverages information from the SMT solver to split where most complexity lies in the search. We implemented our algorithm by modifying Corral , the verifier used by Microsoft’s Static Driver Verifier (SDV), and evaluate it on a series of hard SDV benchmarks.","PeriodicalId":12430,"journal":{"name":"Formal Methods in System Design","volume":"1 1","pages":"1-23"},"PeriodicalIF":0.8,"publicationDate":"2020-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46923223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Incremental column-wise verification of arithmetic circuits using computer algebra.","authors":"Daniela Kaufmann, Armin Biere, Manuel Kauers","doi":"10.1007/s10703-018-00329-2","DOIUrl":"10.1007/s10703-018-00329-2","url":null,"abstract":"<p><p>Verifying arithmetic circuits and most prominently multiplier circuits is an important problem which in practice still requires substantial manual effort. The currently most effective approach uses polynomial reasoning over pseudo boolean polynomials. In this approach a word-level specification is reduced by a Gröbner basis which is implied by the gate-level representation of the circuit. This reduction returns zero if and only if the circuit is correct. We give a rigorous formalization of this approach including soundness and completeness arguments. Furthermore we present a novel incremental column-wise technique to verify gate-level multipliers. This approach is further improved by extracting full- and half-adder constraints in the circuit which allows to rewrite and reduce the Gröbner basis. We also present a new technical theorem which allows to rewrite local parts of the Gröbner basis. Optimizing the Gröbner basis reduces computation time substantially. In addition we extend these algebraic techniques to verify the equivalence of bit-level multipliers without using a word-level specification. Our experiments show that regular multipliers can be verified efficiently by using off-the-shelf computer algebra tools, while more complex and optimized multipliers require more sophisticated techniques. We discuss in detail our complete verification approach including all optimizations.</p>","PeriodicalId":12430,"journal":{"name":"Formal Methods in System Design","volume":"56 1","pages":"22-54"},"PeriodicalIF":0.7,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7691315/pdf/","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"38341195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
César Sánchez, Gerardo Schneider, Wolfgang Ahrendt, E. Bartocci, Domenico Bianculli, C. Colombo, Yliès Falcone, Adrian Francalanza, S. Krstic, João M. Lourenço, D. Ničković, Gordon J. Pace, J. Rufino, Julien Signoles, Dmitriy Traytel, Alexander Weiss
{"title":"Correction to: A survey of challenges for runtime verification from advanced application domains (beyond software)","authors":"César Sánchez, Gerardo Schneider, Wolfgang Ahrendt, E. Bartocci, Domenico Bianculli, C. Colombo, Yliès Falcone, Adrian Francalanza, S. Krstic, João M. Lourenço, D. Ničković, Gordon J. Pace, J. Rufino, Julien Signoles, Dmitriy Traytel, Alexander Weiss","doi":"10.1007/s10703-019-00343-y","DOIUrl":"https://doi.org/10.1007/s10703-019-00343-y","url":null,"abstract":"","PeriodicalId":12430,"journal":{"name":"Formal Methods in System Design","volume":"55 1","pages":"72 - 72"},"PeriodicalIF":0.8,"publicationDate":"2019-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10703-019-00343-y","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43252715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pavel Jancík, J. Kofroň, Leonardo S. Alt, Grigory Fedyukovich, A. Hyvärinen, N. Sharygina
{"title":"Exploiting partial variable assignment in interpolation-based model checking","authors":"Pavel Jancík, J. Kofroň, Leonardo S. Alt, Grigory Fedyukovich, A. Hyvärinen, N. Sharygina","doi":"10.1007/s10703-019-00342-z","DOIUrl":"https://doi.org/10.1007/s10703-019-00342-z","url":null,"abstract":"","PeriodicalId":12430,"journal":{"name":"Formal Methods in System Design","volume":"55 1","pages":"33 - 71"},"PeriodicalIF":0.8,"publicationDate":"2019-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10703-019-00342-z","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48058371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}