2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines最新文献

A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design 可重构建筑设计的一种新的可证明边界

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-08-01 DOI: 10.1109/FPL.2006.311261

Alastair M. Smith, G. Constantinides, P. Cheung

引用次数: 0

COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs fpga中动态模块重构的通信方法

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.32

S. Koh, O. Diessel

引用次数: 22

Integrating FPGA Acceleration into the Protomol Molecular Dynamics Code: Preliminary Report 集成FPGA加速到Protomol分子动力学代码:初步报告

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.52

Y. Gu, T. Court, M. Herbordt

引用次数: 1

A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture 一种用于SuperCISC体系结构的低能量可重构结构

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1166/jolpe.2006.073

Gayatri Mehta, J. Stander, Joshua M. Lucas, R. Hoare, Brady Hunsaker, A. Jones

{"title":"A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture","authors":"Gayatri Mehta, J. Stander, Joshua M. Lucas, R. Hoare, Brady Hunsaker, A. Jones","doi":"10.1166/jolpe.2006.073","DOIUrl":"https://doi.org/10.1166/jolpe.2006.073","url":null,"abstract":"Hardware acceleration using field programmable gate arrays (FPGAs) has become increasingly popular for computationally intensive digital signal processing (DSP) applications. Unfortunately, while FPGAs have a reasonably tractable computer aided design (CAD) flow and performance, they have poor power characteristics when compared to direct application specific integrated circuit (ASIC) fabrication. ASICs exhibit better performance and power than FPGAs, but require complex CAD and large non-recurring engineering (NRE) costs. A reconfigurable device that exhibits ASIC-like power characteristics and FPGA-like costs and tool support is desirable to fill this void. Several coarse-grained fabric architectures proposed during the last decade have been focused on performance and area-efficient architectural techniques. Even though power is becoming one of the critical design concerns for semiconductor industry, this issue has not been adequately addressed in the existing coarse-grained fabric architectures. In this paper, a low-power and high-performance hardware acceleration engine for DSP style applications is described. This reconfigurable fabric model is generic and parameterizable allowing design parameters to be adjusted within the architecture. The impact of varying different design parameters such as functional unit granularity, and multiplexer cardinality are studied for their implications on power and performance. The low-power fabric was designed to operate within the SuperCISC processor architecture designed at the University of Pittsburgh","PeriodicalId":123057,"journal":{"name":"2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129691206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

An Optimized Finite Difference Computing Engine on FPGAs 基于fpga的优化有限差分计算引擎

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.24

Chuan He, Guan Qin, Mi Lu, Wei Zhao

{"title":"An Optimized Finite Difference Computing Engine on FPGAs","authors":"Chuan He, Guan Qin, Mi Lu, Wei Zhao","doi":"10.1109/FCCM.2006.24","DOIUrl":"https://doi.org/10.1109/FCCM.2006.24","url":null,"abstract":"Time domain or frequency domain Finite Difference (FD) methods are one of the most popular numerical modelling techniques in the solution of scientific and engineering problems. However, these simulations are still time-consuming and cannot be used routinely except in institutes that can afford the high cost of running and maintaining supercomputers or large PC-cluster systems. In this paper, we present an efficient implementation of FPGA-based FD computing engine using acoustic wave modeling problems as an example. Instead of following the formal high-order FD expressions with standard IEEE-754 compliant floating-point multipliers and adders, we propose a new class of optimized FD schemes, whose FD coefficients are optimized to be only a few binary bits so that much fewer Logic Cell (LC) resources or on-chip multipliers are needed without deteriorating numerical accuracy criterions. Furthermore, we simplify the implementation of following floatingpoint summations by group-alignment technology. A floating-point/fixed-point hybrid accumulator with similar relative and absolute rounding errors now replaces the conventional costly floating-point adder tree.","PeriodicalId":123057,"journal":{"name":"2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127968368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Switch Box Architectures for Three-Dimensional FPGAs 三维fpga的开关盒架构

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.66

Aman Gayasen, N. Vijaykrishnan, M. Kandemir, Arifur Rahman

引用次数: 6

A Co-Verification Tool for a High Level Language Compiler for FPGAs fpga高级语言编译器的协同验证工具

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.6

C. Ross, A. Böhm

引用次数: 0

A case study in porting a production scientific supercomputing application to a reconfigurable computer 将生产科学超级计算应用程序移植到可重构计算机的案例研究

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.5

V. Kindratenko, D. Pointer

引用次数: 85

A Field Programmable RFID Tag and Associated Design Flow 现场可编程RFID标签及其相关设计流程

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.7

A. Jones, R. Hoare, S. Dontharaju, S. Tung, Ralph Sprang, Joshua Fazekas, J. T. Cain, M. Mickle

{"title":"A Field Programmable RFID Tag and Associated Design Flow","authors":"A. Jones, R. Hoare, S. Dontharaju, S. Tung, Ralph Sprang, Joshua Fazekas, J. T. Cain, M. Mickle","doi":"10.1109/FCCM.2006.7","DOIUrl":"https://doi.org/10.1109/FCCM.2006.7","url":null,"abstract":"Current radio frequency identification (RFID) systems generally have long design times and low tolerance to changes in specification. This paper describes a field programmable, low-power active RFID tag, and its associated specification and automated design flow. RFID primitives to be supported by the tag are enumerated with RFID macros, or assembly-like descriptions of the tag operations. From these, the RFID preprocessor generates templates automatically. The behavior of each RFID primitive is specified using ANSI C in the template. The resulting file is compiled by the RFID compiler. A smart buffer sits between the transceiver and the tag controller, to detect whether incoming packets are intended for the tag. By doing so, the main controller may remain powered down to reduce power consumption. Two system-on-a-chip implementation strategies are presented. First, a microprocessor based system for which a C program is automatically generated. The second includes a block of low-power FPGA logic. The user supplied RFID logic in ANSI-C is automatically converted into combinational VHDL by the RFID compiler. Based on a test program, the processors required 183, 43, and 19 muJ per transaction for StrongARM, XScale, and EISC processors, respectively. By replacing the processor with a Coolrunner II, the controller can be reduced to 1.11 nJ per transaction","PeriodicalId":123057,"journal":{"name":"2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124973135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Highly Efficient String Matching Circuit for IDS with FPGA 基于FPGA的IDS高效字符串匹配电路

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.51

T. Katashita, A. Maeda, K. Toda, Y. Yamaguchi

引用次数: 9