2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines最新文献_第7页

Automated Generation of Hardware Accelerators with Direct Memory Access from ANSI/ISO Standard C Functions 使用ANSI/ISO标准C函数直接访问内存的硬件加速器的自动生成

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.28

David J. Lau, O. Pritchard, P. Molson

引用次数: 68

Generating Parametrised Hardware Libraries from Higher-Order Descriptions 从高阶描述生成参数化硬件库

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.44

O. Pell, W. Luk

引用次数: 0

Defect-Tolerant Nanocomputing Using Bloom Filters 使用Bloom过滤器的容错纳米计算

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.35

Gang Wang, W. Gong, R. Kastner

引用次数: 5

A Type Architecture for Hybrid Micro-Parallel Computers 混合微并行计算机的类型体系结构

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-02-22 DOI: 10.1145/1117201.1117243

Benjamin Ylvisaker, B. V. Essen, C. Ebeling

{"title":"A Type Architecture for Hybrid Micro-Parallel Computers","authors":"Benjamin Ylvisaker, B. V. Essen, C. Ebeling","doi":"10.1145/1117201.1117243","DOIUrl":"https://doi.org/10.1145/1117201.1117243","url":null,"abstract":"Platform FPGAs that integrate sequential processors with a spatial fabric have become prevalent. While these hybrid architectures ease the burden of integrating sequential and spatial code in a single application, programming them, and particularly their spatial fabrics remains challenging. The difficulty arises in part from the lack of an agreed upon computational model and family of programming languages. In addition, moving algorithms into hardware is an arcane art far removed from the experience of most programmers. To address this challenge, we present a new type architecture, an abstract model analogous to the von Neumann machine for sequential computers, that can serve as common ground for algorithm designers, language designers, and hardware architects. We show that many parallel architectures, including platform FPGAs, are implementations of this type architecture. Using examples from a variety of application domains, we show how algorithms can be analyzed to estimate their performance on implementations of this type architecture. This analysis is done without having to delve into the details of any architecture in particular. Finally, we describe some of the common features of languages designed for expressing micro-parallelism, highlighting connections with the type architecture","PeriodicalId":123057,"journal":{"name":"2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131178229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11