Generating Parametrised Hardware Libraries from Higher-Order Descriptions

O. Pell, W. Luk
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Abstract

The Quartz framework allows the generation of parametrised high-performance placed IP cores from higher level descriptions. Circuits are described in the Quartz language, which provides advanced features such as polymorphism, overloading, higher-order combinators and formal reasoning while supporting precise and flexible control of layout for efficient FPGA design. Our compiler transforms Quartz descriptions into VHDL libraries, maintaining design parametrisation and generating placement constraints to maximise performance, increasing clock frequency by up to 25%
从高阶描述生成参数化硬件库
Quartz框架允许从更高级别的描述生成参数化的高性能放置IP内核。电路是用石英语言描述的,它提供了先进的功能,如多态性,过载,高阶组合子和形式推理,同时支持精确和灵活的布局控制,以实现高效的FPGA设计。我们的编译器将Quartz描述转换为VHDL库,保持设计参数化并生成放置约束,以最大限度地提高性能,将时钟频率提高高达25%
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