可重构建筑设计的一种新的可证明边界

Alastair M. Smith, G. Constantinides, P. Cheung
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引用次数: 0

摘要

本文研究了形式化优化方法在混合粒度fpga设计中的应用。特别是,作者研究了异构元素的适当混合和平面图:乘法器,ram和基于lut的逻辑,以便在给定固定硅预算的情况下最大化一组DSP基准应用程序的性能。作者通过提出一组新的启发式方法扩展了我们以前的数学规划框架,能够提供可实现的可重构与固定逻辑性能比的上界。研究结果首次量化了乘数器和RAM块在系统环境中的最佳性能/面积增强能力,并表明在使用最佳技术映射时,通过重新组织设备平面图,Virtex II只能获得最小的性能优势
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design
This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, the authors investigate the appropriate mix and floorplan of heterogeneous elements: multipliers, RAMs, and LUT-based logic, in order to maximise the performance of a set of DSP benchmark applications, given a fixed silicon budget. The authors extend our previous mathematical programming framework by proposing a novel set of heuristics, capable of providing upper bounds on the achievable reconfigurable-to-fixed-logic performance ratio. The results provide, for the first time, quantifications of the optimal performance/area-enhancing capability of multipliers and RAM blocks within a system context, and indicate that only a minimal performance benefit can be achieved over Virtex II by re-organising the device floorplan, when using optimal technology mapping
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