A Field Programmable RFID Tag and Associated Design Flow

A. Jones, R. Hoare, S. Dontharaju, S. Tung, Ralph Sprang, Joshua Fazekas, J. T. Cain, M. Mickle
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引用次数: 18

Abstract

Current radio frequency identification (RFID) systems generally have long design times and low tolerance to changes in specification. This paper describes a field programmable, low-power active RFID tag, and its associated specification and automated design flow. RFID primitives to be supported by the tag are enumerated with RFID macros, or assembly-like descriptions of the tag operations. From these, the RFID preprocessor generates templates automatically. The behavior of each RFID primitive is specified using ANSI C in the template. The resulting file is compiled by the RFID compiler. A smart buffer sits between the transceiver and the tag controller, to detect whether incoming packets are intended for the tag. By doing so, the main controller may remain powered down to reduce power consumption. Two system-on-a-chip implementation strategies are presented. First, a microprocessor based system for which a C program is automatically generated. The second includes a block of low-power FPGA logic. The user supplied RFID logic in ANSI-C is automatically converted into combinational VHDL by the RFID compiler. Based on a test program, the processors required 183, 43, and 19 muJ per transaction for StrongARM, XScale, and EISC processors, respectively. By replacing the processor with a Coolrunner II, the controller can be reduced to 1.11 nJ per transaction
现场可编程RFID标签及其相关设计流程
当前的射频识别(RFID)系统通常设计时间长,对规格变化的容忍度低。本文介绍了一种现场可编程、低功耗有源RFID标签及其相关规范和自动化设计流程。标签支持的RFID原语是用RFID宏或类似于程序集的标签操作描述来枚举的。从这些模板中,RFID预处理器自动生成模板。每个RFID原语的行为在模板中使用ANSI C指定。生成的文件由RFID编译器编译。在收发器和标签控制器之间有一个智能缓冲区,用于检测传入的数据包是否用于标签。这样,主控制器可能处于未上电状态,以降低功耗。提出了两种片上系统的实现策略。首先,一个基于微处理器的系统,它可以自动生成C程序。第二个包括一个低功耗FPGA逻辑块。用户在ANSI-C中提供的RFID逻辑由RFID编译器自动转换为组合VHDL。基于一个测试程序,对于StrongARM、XScale和EISC处理器,每个事务分别需要183、43和19 muJ。通过将处理器替换为Coolrunner II,控制器可以减少到每个事务1.11 nJ
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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