Switch Box Architectures for Three-Dimensional FPGAs

Abstract

In this paper, the authors explore six 3D switch box (SB) topologies for the case when the vias are fewer than the horizontal wires. Using detailed area and delay models, we estimate their impact on FPGA area, delay, and area-delay product. The results indicate that the area-delay product (ADP) depends heavily on the SB topology: our best SB reduces ADP by 9% compared to the subset SB