三维fpga的开关盒架构

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI:10.1109/FCCM.2006.66

Aman Gayasen, N. Vijaykrishnan, M. Kandemir, Arifur Rahman

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引用次数: 6

摘要

在本文中，作者探讨了六种三维开关箱(SB)拓扑结构，用于过孔小于水平导线的情况。使用详细的面积和延迟模型，我们估计了它们对FPGA面积、延迟和区域延迟产品的影响。结果表明，区域延迟积(ADP)在很大程度上依赖于SB拓扑:与子集SB相比，我们的最佳SB将ADP降低了9%

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Switch Box Architectures for Three-Dimensional FPGAs

In this paper, the authors explore six 3D switch box (SB) topologies for the case when the vias are fewer than the horizontal wires. Using detailed area and delay models, we estimate their impact on FPGA area, delay, and area-delay product. The results indicate that the area-delay product (ADP) depends heavily on the SB topology: our best SB reduces ADP by 9% compared to the subset SB

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来源期刊

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

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