2021 22nd International Symposium on Quality Electronic Design (ISQED)最新文献_第9页

Sandbox Detection Using Hardware Side Channels 使用硬件侧通道的沙盒检测

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424260

Yehonatan Lusky, A. Mendelson

引用次数: 3

Profiled Power-Analysis Attacks by an Efficient Architectural Extension of a CNN Implementation 通过CNN实现的高效架构扩展来分析功率分析攻击

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424361

Soroor Ghandali, S. Ghandali, Sara Tehranipoor

{"title":"Profiled Power-Analysis Attacks by an Efficient Architectural Extension of a CNN Implementation","authors":"Soroor Ghandali, S. Ghandali, Sara Tehranipoor","doi":"10.1109/ISQED51717.2021.9424361","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424361","url":null,"abstract":"In a recent line of works, several masking and unmasking AES design have been proposed to secure hardware implementations against power-analysis techniques. Although Machine-learning profiling techniques have been successful in security testing during the last years, evaluation of hardware security still requires improvement because of the growing complexity of leakage models against profiled side-channel attacks. In this paper, we propose an improved profiling method to exploit the power consumption of complex cryptographic functions based on Deep-Learning. In order to learn the 256-class Deep neural network of an AES-128, we build successful Convolutional Neural Networks to break its implementation. It has been shown by our experiments that our model achieved a success rate of $ge 99$% even with a single trace using Keras library with Tensorflow. For the sake of completeness, we investigate the correct ”key rank” according to the number of traces and as a further performance measure, we use ”recall” metric when attacking the third AES SBox. Our model reaches the key rank $le 10$ with the recall metric $ge 0.99$.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114349701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Regularization-Free Structural Pruning for GPU Inference Acceleration 用于GPU推理加速的无正则化结构剪枝

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424299

Chuliang Guo, Yanbing Yang, Li Zhang, Shaodi Wang, He Li, Keyu Long, Xunzhao Yin, Cheng Zhuo

引用次数: 0

Flush-Reload Attack and its Mitigation on an FPGA Based Compressed Cache Design 基于FPGA压缩缓存设计的Flush-Reload攻击及其缓解

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424252

Prashant Mata, Nanditha P. Rao

{"title":"Flush-Reload Attack and its Mitigation on an FPGA Based Compressed Cache Design","authors":"Prashant Mata, Nanditha P. Rao","doi":"10.1109/ISQED51717.2021.9424252","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424252","url":null,"abstract":"Several micro-architectural components such as caches, branch predictors and prefetchers are known to assist in side-channel data leaks. Side-channel attacks recover secret data by observing the timing behavior while the victim process accesses the cache or the memory. In this paper, we explore the impact of a Flush-Reload attack in the presence of a cache compression scheme. Cache compression technique increases the effective size of the cache through compression and appropriate placement of the compressed data blocks. We integrate the compressed cache design with a RISC-V processor core on an FPGA. We implement the Flush-Reload attack and find that the impact of the attack on a compressed cache scheme is likely to be weaker than that of an uncompressed design. To the best of our knowledge, this is the first attempt at understanding the role of side-channel attacks on a compressed cache design in hardware. We further explore the possibility of using a variable clock logic and observe that it reduces the effectiveness of the attack by 30 to 50%. However, this scheme could impact the cache performance by up to 2.9 times.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114899390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

True Random Number Generation using Latency Variations of Commercial MRAM Chips 利用商用MRAM芯片的延迟变化生成真随机数

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-01 DOI: 10.1109/ISQED51717.2021.9424346

F. Ferdaus, B. M. S. B. Talukder, Mehdi Sadi, Md. Tauhidur Rahman

引用次数: 4

Achieving Wave Pipelining in Spin Wave Technology 实现自旋波技术中的波流水线

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-03-18 DOI: 10.1109/ISQED51717.2021.9424264

A. Mahmoud, Frederic Vanderveken, C. Adelmann, F. Ciubotaru, S. Hamdioui, S. Cotofana

{"title":"Achieving Wave Pipelining in Spin Wave Technology","authors":"A. Mahmoud, Frederic Vanderveken, C. Adelmann, F. Ciubotaru, S. Hamdioui, S. Cotofana","doi":"10.1109/ISQED51717.2021.9424264","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424264","url":null,"abstract":"By their very nature, voltage/current excited Spin Waves (SWs) propagate through waveguides without consuming noticeable power. If SW excitation is performed by the continuous application of voltages/currents to the input, which is usually the case, the overall energy consumption is determined by the transducer power and the circuit critical path delay, which leads to high energy consumption because of SWs slowness. However, if transducers are operated in pulses the energy becomes circuit delay independent and it is mainly determined by the transducer power and delay, thus pulse operation should be targeted. In this paper, we utilize a 3-input Majority gate (MAJ) to investigate the Continuous Mode Operation (CMO), and Pulse Mode Operation (PMO). Moreover, we validate CMO and PMO 3-input Majority gate by means of micromagnetic simulations. Furthermore, we evaluate and compare the CMO and PMO Majority gate implementations in term of energy. The results indicate that PMO diminishes MAJ gate energy consumption by a factor of 18. In addition, we describe how PMO can open the road towards the utilization of the Wave Pipelining (WP) concept in SW circuits. We validate the WP concept by means of micromagnetic simulations and we evaluate its implications in term of throughput. Our evaluation indicates that for a circuit formed by four cascaded MAJ gates WP increases the throughput by 3.6x.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123838142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Brightening the Optical Flow through Posit Arithmetic 利用位算法增强光流

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-01-17 DOI: 10.1109/ISQED51717.2021.9424360

Vinay Saxena, A. Reddy, J. Neudorfer, J. Gustafson, Sangeeth Nambiar, R. Leupers, Farhad Merchant

{"title":"Brightening the Optical Flow through Posit Arithmetic","authors":"Vinay Saxena, A. Reddy, J. Neudorfer, J. Gustafson, Sangeeth Nambiar, R. Leupers, Farhad Merchant","doi":"10.1109/ISQED51717.2021.9424360","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424360","url":null,"abstract":"As new technologies are invented, their commercial viability needs to be carefully examined along with their technical merits and demerits. The ${posit}^{TM}$ data format, proposed as a drop-in replacement for IEEE $754 ^{TM}$ float format, is one such invention that requires extensive theoretical and experimental study to identify products that can benefit from the advantages of posits for specific market segments. In this paper, we present an extensive empirical study of posit-based arithmetic vis-à-vis IEEE 754 compliant arithmetic for the optical flow estimation method called Lucas-Kanade (LuKa). First, we use SoftPosit and SoftFloat format emulators to perform an empirical error analysis of the LuKa method. Our study shows that the average error in LuKa with SoftPosit is an order of magnitude lower than LuKa with SoftFloat. We then present the integration of the hardware implementation of a posit adder and multiplier in a RISC-V open-source platform. We make several recommendations, along with the analysis of LuKa in the RISC-V context, for future generation platforms incorporating posit arithmetic units.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"381 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123620698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

CARE: Lightweight Attack Resilient Secure Boot Architecture with Onboard Recovery for RISC-V based SOC CARE:轻量级攻击弹性安全启动架构，支持基于RISC-V的SOC板载恢复

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-01-15 DOI: 10.1109/ISQED51717.2021.9424322

Avani Dave, Nilanjan Banerjee, C. Patel

{"title":"CARE: Lightweight Attack Resilient Secure Boot Architecture with Onboard Recovery for RISC-V based SOC","authors":"Avani Dave, Nilanjan Banerjee, C. Patel","doi":"10.1109/ISQED51717.2021.9424322","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424322","url":null,"abstract":"Recent technological advancements have proliferated the use of small embedded devices for collecting, processing, and transferring the security-critical information. The Internet of Things (IoT) has enabled remote access and control of these network-connected devices. Consequently, an attacker can exploit security vulnerabilities and compromise these devices. In this context, the secure boot becomes a useful security mechanism to verify the integrity and authenticity of the software state of the devices. However, the current secure boot schemes focus on detecting the presence of potential malware on the device but not on disinfecting and restoring the software to a benign state. This manuscript presents CARE - the first secure boot framework that provides malicious code modification attack detection, resilience, and onboard recovery mechanism for the compromised devices. The framework uses a prototype hybrid CARE: Code Authentication and Resilience Engine to verify the integrity and authenticity of the software and restore it to a benign state. It uses Physical Memory Protection (PMP) and other security enchaining techniques of RISC-V processor to provide resilience from modern attacks. The state-of-the-art comparison and performance analysis results indicate that the proposed secure boot framework provides promising resilience and recovery mechanism with very little (8%) performance and resource overhead.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"348 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124293642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Exploring Fault-Energy Trade-offs in Approximate DNN Hardware Accelerators 探索近似DNN硬件加速器中的故障能量权衡

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-01-08 DOI: 10.1109/ISQED51717.2021.9424345

Ayesha Siddique, K. Basu, K. A. Hoque

{"title":"Exploring Fault-Energy Trade-offs in Approximate DNN Hardware Accelerators","authors":"Ayesha Siddique, K. Basu, K. A. Hoque","doi":"10.1109/ISQED51717.2021.9424345","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424345","url":null,"abstract":"Systolic array-based deep neural network (DNN) accelerators have recently gained prominence for their low computational cost. However, their high energy consumption poses a bottleneck to their deployment in energy-constrained devices. To address this problem, approximate computing can be employed at the cost of some tolerable accuracy loss. However, such small accuracy variations may increase the sensitivity of DNNs towards undesired subtle disturbances, such as permanent faults. The impact of permanent faults in accurate DNNs has been thoroughly investigated in the literature. Conversely, the impact of permanent faults in approximate DNN accelerators (AxDNNs) is yet under-explored. The impact of such faults may vary with the fault bit positions, activation functions and approximation errors in AxDNN layers. Such dynamacity poses a considerable challenge to exploring the trade-off between their energy efficiency and fault resilience in AxDNNs. Towards this, we present an extensive layer-wise and bit-wise fault resilience and energy analysis of different AxDNNs, using the state-of-the-art Evoapprox8b signed multipliers. In particular, we vary the stuck-at-0, stuck-at-1 fault-bit positions, and activation functions to study their impact using the most widely used MNIST and Fashion-MNIST datasets. Our quantitative analysis shows that the permanent faults exacerbate the accuracy loss in AxDNNs when compared to the accurate DNN accelerators. For instance, a permanent fault in AxDNNs can lead up to 66% accuracy loss, whereas the same faulty bit can lead to only 9% accuracy loss in an accurate DNN accelerator. Our results demonstrate that the fault resilience in AxDNNs is orthogonal to the energy efficiency.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115104408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators dnn加速器3d - ic的架构、数据流和物理设计含义

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-12-23 DOI: 10.1109/ISQED51717.2021.9424349

J. Joseph, A. Samajdar, Lingjun Zhu, R. Leupers, Syun-Kun Lim, Thilo Pionteck, T. Krishna

引用次数: 3