Flush-Reload Attack and its Mitigation on an FPGA Based Compressed Cache Design

Abstract

Several micro-architectural components such as caches, branch predictors and prefetchers are known to assist in side-channel data leaks. Side-channel attacks recover secret data by observing the timing behavior while the victim process accesses the cache or the memory. In this paper, we explore the impact of a Flush-Reload attack in the presence of a cache compression scheme. Cache compression technique increases the effective size of the cache through compression and appropriate placement of the compressed data blocks. We integrate the compressed cache design with a RISC-V processor core on an FPGA. We implement the Flush-Reload attack and find that the impact of the attack on a compressed cache scheme is likely to be weaker than that of an uncompressed design. To the best of our knowledge, this is the first attempt at understanding the role of side-channel attacks on a compressed cache design in hardware. We further explore the possibility of using a variable clock logic and observe that it reduces the effectiveness of the attack by 30 to 50%. However, this scheme could impact the cache performance by up to 2.9 times.