2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献

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An active interference canceler with reduced harmonic response and synthesizer tuning range 具有减少谐波响应和合成器调谐范围的有源干扰消除器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337785
Wei-Gi Ho, V. Singh, Travis Forbes, R. Gharpurey
{"title":"An active interference canceler with reduced harmonic response and synthesizer tuning range","authors":"Wei-Gi Ho, V. Singh, Travis Forbes, R. Gharpurey","doi":"10.1109/RFIC.2015.7337785","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337785","url":null,"abstract":"A feedback-based active interference cancellation technique for reducing interference in a broadband LNA is described. The interference is down-converted to baseband, low-pass filtered, then up-converted and subtracted from the input. Harmonic response in the active canceler is eliminated by using harmonic rejection mixers (HRMs). Furthermore, by configuring the HRMs to provide frequency translation while using the LO fundamental or its harmonics, the span required of the frequency synthesizer for driving the HRMs is reduced. Implemented in a 65 nm process, the proposed technique shows 8-13 dB improvement in blocker 1-dB compression.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132171643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 380µW Rx, 2.6mW Tx 433MHz FSK transceiver with a 102dB link budget and bit-level duty cycling 380µW Rx, 2.6mW Tx 433MHz FSK收发器,链路预算102dB,位级占空比
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337732
N. Roberts, Michael Kines, D. Wentzloff
{"title":"A 380µW Rx, 2.6mW Tx 433MHz FSK transceiver with a 102dB link budget and bit-level duty cycling","authors":"N. Roberts, Michael Kines, D. Wentzloff","doi":"10.1109/RFIC.2015.7337732","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337732","url":null,"abstract":"This paper presents a low-power, long-range 433MHz transceiver designed for 2-FSK modulation at 1kbps in 8 different physical channels capable of communicating with a Texas Instruments CC1101. Designed in a 130nm CMOS process with an area of 1.1mm2, the transmitter's output power is 0dBm and the receiver has a sensitivity of -102dBm producing a link budget >100dB and a theoretical range >5km assuming 1/d2 path loss. Low transmitter power is achieved using a 0.5V Class-E PA and low receiver power is achieved by implementing a digitally-assisted demodulator with further power reduction achieved through bit-level duty cycling with an off power of 110nW.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131525292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A low-power 40 Gb/s optical receiver in silicon 低功耗40gb /s硅光接收机
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337768
Z. Xuan, R. Ding, Yang Liu, T. Baehr‐Jones, M. Hochberg, F. Aflatouni
{"title":"A low-power 40 Gb/s optical receiver in silicon","authors":"Z. Xuan, R. Ding, Yang Liu, T. Baehr‐Jones, M. Hochberg, F. Aflatouni","doi":"10.1109/RFIC.2015.7337768","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337768","url":null,"abstract":"A low-power 40 Gb/s optical receiver is reported. The receiver consists of a broadband photodiode followed by a low-noise transimpedance amplifier front-end, a 3-stage Cherry-Hooper limiting amplifier, an output driver, and an offset cancellation network. The photodiode is fabricated in a 0.18 μm Ge-on-SOI process and the electronic chip is fabricated in a 0.13 μm SiGe BiCMOS process. The receiver consumes 77 mW. The output eye diagram has a 100 mV single-ended opening with input photocurrents as low as 120 μApp.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134257602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Highly linear envelope tracking power amplifier with simple correction circuit 具有简单校正电路的高线性包络跟踪功率放大器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337721
Kyunghoon Moon, Jooseung Kim, Sangsu Jin, Byungjoon Park, Yunsung Cho, Min Park, Bumman Kim
{"title":"Highly linear envelope tracking power amplifier with simple correction circuit","authors":"Kyunghoon Moon, Jooseung Kim, Sangsu Jin, Byungjoon Park, Yunsung Cho, Min Park, Bumman Kim","doi":"10.1109/RFIC.2015.7337721","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337721","url":null,"abstract":"In this paper, we propose an envelope tracking (ET) power amplifier (PA) with a simple correction circuit (SCC) for linear operation. The supply dependent AM-AM and AM-PM distortion of an ET PA is linearized by the SCC which is fabricated on chip. The PA and supply modulator are fabricated using I/O device of CMOS 40nm process. For the 9.35-dB peak-to-average-power ratio, 256-QAM IEEE 802.11ah signal, the ET PA delivers a power-added efficiency of 24%, an average output power of 19.4 dBm and an error vector magnitude of -30 dB.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134313544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Design of Lange Couplers with local ground references using SiGe BiCMOS technology for mm-Wave applications 使用SiGe BiCMOS技术为毫米波应用设计具有本地地面参考的兰格耦合器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337777
S. Wane, L. Leyssenne, O. Tesson, O. Doussin, D. Bajon, D. Lesenechal, T. Dinh, M. P. van Heijden, R. Pijper, P. Magnée, P. Descamps, A. Erdem
{"title":"Design of Lange Couplers with local ground references using SiGe BiCMOS technology for mm-Wave applications","authors":"S. Wane, L. Leyssenne, O. Tesson, O. Doussin, D. Bajon, D. Lesenechal, T. Dinh, M. P. van Heijden, R. Pijper, P. Magnée, P. Descamps, A. Erdem","doi":"10.1109/RFIC.2015.7337777","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337777","url":null,"abstract":"SiGe BiCMOS design solutions for Lange Couplers operating in the mm-Wave domain are proposed. Various circuit topologies are designed, fabricated, and experimentally compared in terms of their RF performances. Effect of grounding strategies and influence of DTI pattering are studied both for CPS and CPW topologies to evaluate dependence of obtained RF performances on Die back-side grounding strategies. Perspectives for physics-based broadband equivalent circuit model extraction are proposed for lumped elements implementation of Lange Couplers using custom variation-aware RLC library elements.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134435419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 10 GHz delay line frequency discriminator and PD/CP based CMOS phase noise measurement circuit with −138.6 dBc/Hz sensitivity at 1 MHz offset 一种10 GHz延迟线鉴频器和基于PD/CP的CMOS相位噪声测量电路,在1 MHz偏移时灵敏度为−138.6 dBc/Hz
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337705
Shilei Hao, T. Hu, Q. Gu
{"title":"A 10 GHz delay line frequency discriminator and PD/CP based CMOS phase noise measurement circuit with −138.6 dBc/Hz sensitivity at 1 MHz offset","authors":"Shilei Hao, T. Hu, Q. Gu","doi":"10.1109/RFIC.2015.7337705","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337705","url":null,"abstract":"This paper presents a delay line frequency discriminator (FD) and phase detector (PD)/charge pump (CP) based phase noise measurement (PNM) circuit to achieve wide bandwidth, great sensitivity and reliable integration at 10 GHz. PD/CP based phase noise detection makes it insensitive to environment and coupling noises. A delay-locked loop (DLL) is designed to align the PD input phases and a DC offset cancellation circuit is embedded to overcome circuit mismatches, which make the PNM self-calibrated. This PNM demonstrates -61/-81 dBc single tone sensitivity and -110.35/-138.60 dBc/Hz phase noise sensitivity at 100 kHz/1 MHz offset, respectively. The phase noise measurement bandwidth is 200 MHz, which is determined by the off-chip SAW filter bandwidth. This proof-of-concept design is fabricated in a 65 nm CMOS technology with the chip area of 1.5 mm × 1.3 mm. The core circuit consumes 15.2 mW power.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133338848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A fully-integrated reconfigurable transceiver for narrowband wireless communication in 180nm CMOS 一种完全集成的可重构收发器,用于180nm CMOS窄带无线通信
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337731
Zheng Song, Xiliang Liu, Xiaokun Zhao, Qiongbing Liu, Zongming Jin, Yun Yin, Yichuang Sun, B. Chi
{"title":"A fully-integrated reconfigurable transceiver for narrowband wireless communication in 180nm CMOS","authors":"Zheng Song, Xiliang Liu, Xiaokun Zhao, Qiongbing Liu, Zongming Jin, Yun Yin, Yichuang Sun, B. Chi","doi":"10.1109/RFIC.2015.7337731","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337731","url":null,"abstract":"A fully integrated reconfigurable transceiver (TRX) in 180nm CMOS for 750-960MHz narrowband applications is presented. The low-cost TRX consists of a low-IF receiver with 180 kHz signal bandwidth, a digital polar transmitter with 3.75 kHz signal bandwidth and a fractional-N frequency synthesizer. The receiver features a passive current mode mixer to improve the linearity and avoid the noise degradation due to the 1/f noise. The on-chip I/Q mismatch calibration is introduced to improve the image rejection ratio (IRR). The Inverse Class-D power amplifier (PA) is integrated into the transmitter to achieve high output power and efficiency, and the pre-distortion is exploited to realize the DPA linearization. Besides, the digital transmitter performs the power output by digitally controlling the DPA unit array. In order to compensate for PVT variations, the DCOC, I/Q mismatch, AFC and filter frequency tuning are all integrated in the transceiver. The RX achieves 5.1dB NF, 48dB IRR and 60dB gain dynamic range with 1dB step. The DPA provides the maximum 24.2dBm output power with 28.9% PAE. Furthermore, the TX demonstrates 4.9% EVM for 891MHz DQPSK signals at 19.09dBm output power.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122743612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 79 GHz gm-boosted sub-harmonic mixer with high conversion gain in 65nm CMOS 基于65nm CMOS的高转换增益的79 GHz gm增强次谐波混频器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337692
Jingyu Jang, Juntaek Oh, Songcheol Hong
{"title":"A 79 GHz gm-boosted sub-harmonic mixer with high conversion gain in 65nm CMOS","authors":"Jingyu Jang, Juntaek Oh, Songcheol Hong","doi":"10.1109/RFIC.2015.7337692","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337692","url":null,"abstract":"In this paper, a 79 GHz gm-boosted sub-harmonic mixer with high conversion gain is presented. As a gm-boosting technique, a transformer based feedback network with an NMOS bleeding path is proposed to achieve high conversion gain. The differential LO-driven sub-harmonic mixer has a simple structure and operates at low LO power. The measurement results show a conversion gain of 1.6 dB at a LO power of -5 dBm, a noise figure of 13 dB, and a 2LO-to-RF isolation of 38 dB. The power consumption of the sub-harmonic mixer is 12 mW. The circuit was fabricated using 65-nm CMOS technology with a chip area of 0.69×0.45 mm2.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125140412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A 60 GHz single-chip 256-element wafer-scale phased array with EIRP of 45 dBm using sub-reticle stitching 60 GHz单片256元晶圆级相控阵,EIRP为45 dBm,采用亚十字拼接
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337695
S. Zihir, O. Gurbuz, A. Karroy, S. Raman, Gabriel M. Rebeiz
{"title":"A 60 GHz single-chip 256-element wafer-scale phased array with EIRP of 45 dBm using sub-reticle stitching","authors":"S. Zihir, O. Gurbuz, A. Karroy, S. Raman, Gabriel M. Rebeiz","doi":"10.1109/RFIC.2015.7337695","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337695","url":null,"abstract":"This paper presents a 60 GHz wafer-scale transmit phased-array with 256-elements spaced λ/2 apart in the x and y directions, and occupying an area of 4.14×4.2 cm2 (1740 mm2). The phased array is built using independent RF, transmission-line and control circuit blocks which are stitched together to form an aggregate chip which is much larger than a standard reticle (22×22 mm2). This method allows for a wafer-scale design and can be extended to any size and any shape (rectangular, hexagonal, etc.) up to the edge of the wafer. The blocks include high-efficiency on-wafer antennas, phased-array channels with 3-bits amplitude and 5-bits phase control together with an amplifier having an output power of +3 dBm at 60 GHz. Also, a highly redundant RF distribution network is synthesized from several stitched blocks for improved yield, and the control blocks have redundant SPI control and power strips, also for improved yield. The 256-element array results in a half-power beamwidth of 6° in the E- and H-planes, a directivity of 29 dB, and scans to +/- 55° in the E- and H-planes with near-ideal patterns and a cross-polarization level of <;-25 dB. The measured EIRP is 45 dBm at 61 GHz and with a 3-dB bandwidth from 58 to 64 GHz. To our knowledge, this is the largest single-chip phased-array ever developed and allows the construction of large-scale (1000+ elements) phased-array systems, either on a single wafer or by assembling several of these chips together.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126923037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
A fully integrated 0.18um CMOS UWB SoC for wireless body area network applications 完全集成的0.18um CMOS UWB SoC,适用于无线体域网络应用
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337751
M. Park, W. Chang, Kyoung Hak Lee, Dong-Sun Kim, Taeho Hwang, Y. Eo
{"title":"A fully integrated 0.18um CMOS UWB SoC for wireless body area network applications","authors":"M. Park, W. Chang, Kyoung Hak Lee, Dong-Sun Kim, Taeho Hwang, Y. Eo","doi":"10.1109/RFIC.2015.7337751","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337751","url":null,"abstract":"A fully integrated 3 - 5GHz CMOS transceiver SoC for WBAN is presented in this paper. To achieve the low power and low complexity, OOK receiver architecture and the digital impulse generator are employed. For the rejection of the undesired interferers, the tunable RF notch filter is integrated and measured results show more than 9 dB improvement of the sensitivity. The measured energy efficiency of transmitter and the receiver sensitivity are 20.6 pJ/bit and -86.5 dBm, respectively.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129395524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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