2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献_第7页

An active interference canceler with reduced harmonic response and synthesizer tuning range 具有减少谐波响应和合成器调谐范围的有源干扰消除器

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337785

Wei-Gi Ho, V. Singh, Travis Forbes, R. Gharpurey

引用次数: 2

A 380µW Rx, 2.6mW Tx 433MHz FSK transceiver with a 102dB link budget and bit-level duty cycling 380µW Rx, 2.6mW Tx 433MHz FSK收发器，链路预算102dB，位级占空比

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337732

N. Roberts, Michael Kines, D. Wentzloff

引用次数: 6

A low-power 40 Gb/s optical receiver in silicon 低功耗40gb /s硅光接收机

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337768

Z. Xuan, R. Ding, Yang Liu, T. Baehr‐Jones, M. Hochberg, F. Aflatouni

引用次数: 7

Highly linear envelope tracking power amplifier with simple correction circuit 具有简单校正电路的高线性包络跟踪功率放大器

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337721

Kyunghoon Moon, Jooseung Kim, Sangsu Jin, Byungjoon Park, Yunsung Cho, Min Park, Bumman Kim

引用次数: 7

Design of Lange Couplers with local ground references using SiGe BiCMOS technology for mm-Wave applications 使用SiGe BiCMOS技术为毫米波应用设计具有本地地面参考的兰格耦合器

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337777

S. Wane, L. Leyssenne, O. Tesson, O. Doussin, D. Bajon, D. Lesenechal, T. Dinh, M. P. van Heijden, R. Pijper, P. Magnée, P. Descamps, A. Erdem

引用次数: 6

A 10 GHz delay line frequency discriminator and PD/CP based CMOS phase noise measurement circuit with −138.6 dBc/Hz sensitivity at 1 MHz offset 一种10 GHz延迟线鉴频器和基于PD/CP的CMOS相位噪声测量电路，在1 MHz偏移时灵敏度为−138.6 dBc/Hz

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337705

Shilei Hao, T. Hu, Q. Gu

引用次数: 8

A fully-integrated reconfigurable transceiver for narrowband wireless communication in 180nm CMOS 一种完全集成的可重构收发器，用于180nm CMOS窄带无线通信

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337731

Zheng Song, Xiliang Liu, Xiaokun Zhao, Qiongbing Liu, Zongming Jin, Yun Yin, Yichuang Sun, B. Chi

{"title":"A fully-integrated reconfigurable transceiver for narrowband wireless communication in 180nm CMOS","authors":"Zheng Song, Xiliang Liu, Xiaokun Zhao, Qiongbing Liu, Zongming Jin, Yun Yin, Yichuang Sun, B. Chi","doi":"10.1109/RFIC.2015.7337731","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337731","url":null,"abstract":"A fully integrated reconfigurable transceiver (TRX) in 180nm CMOS for 750-960MHz narrowband applications is presented. The low-cost TRX consists of a low-IF receiver with 180 kHz signal bandwidth, a digital polar transmitter with 3.75 kHz signal bandwidth and a fractional-N frequency synthesizer. The receiver features a passive current mode mixer to improve the linearity and avoid the noise degradation due to the 1/f noise. The on-chip I/Q mismatch calibration is introduced to improve the image rejection ratio (IRR). The Inverse Class-D power amplifier (PA) is integrated into the transmitter to achieve high output power and efficiency, and the pre-distortion is exploited to realize the DPA linearization. Besides, the digital transmitter performs the power output by digitally controlling the DPA unit array. In order to compensate for PVT variations, the DCOC, I/Q mismatch, AFC and filter frequency tuning are all integrated in the transceiver. The RX achieves 5.1dB NF, 48dB IRR and 60dB gain dynamic range with 1dB step. The DPA provides the maximum 24.2dBm output power with 28.9% PAE. Furthermore, the TX demonstrates 4.9% EVM for 891MHz DQPSK signals at 19.09dBm output power.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122743612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A 79 GHz gm-boosted sub-harmonic mixer with high conversion gain in 65nm CMOS 基于65nm CMOS的高转换增益的79 GHz gm增强次谐波混频器

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337692

Jingyu Jang, Juntaek Oh, Songcheol Hong

引用次数: 16

A 60 GHz single-chip 256-element wafer-scale phased array with EIRP of 45 dBm using sub-reticle stitching 60 GHz单片256元晶圆级相控阵，EIRP为45 dBm，采用亚十字拼接

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337695

S. Zihir, O. Gurbuz, A. Karroy, S. Raman, Gabriel M. Rebeiz

{"title":"A 60 GHz single-chip 256-element wafer-scale phased array with EIRP of 45 dBm using sub-reticle stitching","authors":"S. Zihir, O. Gurbuz, A. Karroy, S. Raman, Gabriel M. Rebeiz","doi":"10.1109/RFIC.2015.7337695","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337695","url":null,"abstract":"This paper presents a 60 GHz wafer-scale transmit phased-array with 256-elements spaced λ/2 apart in the x and y directions, and occupying an area of 4.14×4.2 cm2 (1740 mm2). The phased array is built using independent RF, transmission-line and control circuit blocks which are stitched together to form an aggregate chip which is much larger than a standard reticle (22×22 mm2). This method allows for a wafer-scale design and can be extended to any size and any shape (rectangular, hexagonal, etc.) up to the edge of the wafer. The blocks include high-efficiency on-wafer antennas, phased-array channels with 3-bits amplitude and 5-bits phase control together with an amplifier having an output power of +3 dBm at 60 GHz. Also, a highly redundant RF distribution network is synthesized from several stitched blocks for improved yield, and the control blocks have redundant SPI control and power strips, also for improved yield. The 256-element array results in a half-power beamwidth of 6° in the E- and H-planes, a directivity of 29 dB, and scans to +/- 55° in the E- and H-planes with near-ideal patterns and a cross-polarization level of <;-25 dB. The measured EIRP is 45 dBm at 61 GHz and with a 3-dB bandwidth from 58 to 64 GHz. To our knowledge, this is the largest single-chip phased-array ever developed and allows the construction of large-scale (1000+ elements) phased-array systems, either on a single wafer or by assembling several of these chips together.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126923037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 37

A fully integrated 0.18um CMOS UWB SoC for wireless body area network applications 完全集成的0.18um CMOS UWB SoC，适用于无线体域网络应用

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337751

M. Park, W. Chang, Kyoung Hak Lee, Dong-Sun Kim, Taeho Hwang, Y. Eo

引用次数: 1