A low-power 40 Gb/s optical receiver in silicon

Abstract

A low-power 40 Gb/s optical receiver is reported. The receiver consists of a broadband photodiode followed by a low-noise transimpedance amplifier front-end, a 3-stage Cherry-Hooper limiting amplifier, an output driver, and an offset cancellation network. The photodiode is fabricated in a 0.18 μm Ge-on-SOI process and the electronic chip is fabricated in a 0.13 μm SiGe BiCMOS process. The receiver consumes 77 mW. The output eye diagram has a 100 mV single-ended opening with input photocurrents as low as 120 μApp.