Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)最新文献_第5页

Device optimization for ultra-low power digital sub-threshold operation 超低功耗数字亚阈值操作的器件优化

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013266

B. Paul, A. Raychowdhury, K. Roy

引用次数: 25

A way-halting cache for low-energy high-performance systems 用于低能耗高性能系统的路径中断缓存

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013272

Chuanjun Zhang, F. Vahid, Jun Yang, W. Najjar

{"title":"A way-halting cache for low-energy high-performance systems","authors":"Chuanjun Zhang, F. Vahid, Jun Yang, W. Najjar","doi":"10.1145/1013235.1013272","DOIUrl":"https://doi.org/10.1145/1013235.1013272","url":null,"abstract":"Caches contribute to much of a microprocessor system's power and energy consumption. We have developed a new cache architecture, called a way-halting cache, that reduces energy while imposing no performance overhead. Our way-halting cache is a four-way set-associative cache that stores the four lowest-order bits of all ways' tags into a fully associative memory, which we call the halt tag array. The look-up in the hall tag array is done in parallel with, and is no slower than, the set-index decoding. The hall tag array pre-determines which tags cannot match due to their low-order four bits mismatching. Further accesses to ways with known mismatching tags are then halted, thus saving power. Our halt tag array has an additional feature of using static logic only, rather than dynamic logic used in highly associative caches. We provide data from experiments on 17 benchmarks drawn from MediaBench and Spec 2000, based on our layouts in 0.18 micron CMOS technology, On average, 55% savings of memory-access related energy were obtained over a conventional four-way set-associative cache. We show that energy savings are greater than previous methods, and nearly twice that of highly-associative caches, while imposing no performance overhead and only 2% cache area overhead.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115689593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 45

Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces 有限字内转换码:LCD显示接口的节能总线编码

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013288

S. Salerno, Alberto Bocca, E. Macii, M. Poncino

引用次数: 20

A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach 基于一种新型互补平均值方法的低功耗轨对轨6位闪存ADC

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013300

Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu

引用次数: 16

Application adaptive energy efficient clustered architectures 应用程序自适应节能集群架构

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013318

Diana Marculescu

{"title":"Application adaptive energy efficient clustered architectures","authors":"Diana Marculescu","doi":"10.1145/1013235.1013318","DOIUrl":"https://doi.org/10.1145/1013235.1013318","url":null,"abstract":"As clock frequency and die area increase, achieving energy efficiency, while distributing a low skew, global clock signal becomes increasingly difficult. Challenges imposed by deep-submicron technologies can be alleviated by using a multiple voltage/multiple frequency island design style, otherwise called the globally asynchronous, locally synchronous (GALS) design paradigm. This paper proposes a clustered architecture that enables application-adaptive energy efficiency through the use of dynamic voltage scaling for application code that is rendered non-critical for the overall performance, at run-time. As opposed to task scheduling using dynamic voltage scaling (DVS) that exploits workload variations across applications, our approach targets workload variations within the same application, while on-the fly classifying code as critical or noncritical and adapting to changes in the criticality of such code portions. Our results show that application adaptive variable voltage/variable frequency clustered architectures are up to 22% better in energy and 11% better in energy-delay product than their non-adaptive counterparts, while providing up to 31% more energy savings when compared to DVS applied globally.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116561996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Nanoscale CMOS circuit leakage power reduction by double-gate device 采用双栅器件降低纳米级CMOS电路漏功率

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013267

Keunwoo Kim, K. Das, R. Joshi, C. Chuang

引用次数: 21

Any-time probabilistic switching model using Bayesian networks 基于贝叶斯网络的任意时间概率切换模型

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013263

Shiva Shankar Ramani, S. Bhanja

引用次数: 16

Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses 延迟线路总线方案:一种低功耗总线方案，用于耦合片上总线

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013257

M. Ghoneima, Y. Ismail

引用次数: 16

Experience with a low power wireless mobile computing platform 具有低功耗无线移动计算平台的使用经验

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013322

V. Raghunathan, T. Pering, R. Want, Alex Nguyen, P. Jensen

引用次数: 65

On optimality of adiabatic switching in MOS energy-recovery circuit MOS能量回收电路中绝热开关的最优性

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013295

Baohua Wang, P. Mazumder

引用次数: 20