2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)最新文献_第2页

A 12.42μA 0.192ppm/°C high PSRR curvature-compensated CMOS bandgap voltage reference 一个12.42μA 0.192ppm/°C的高PSRR曲率补偿CMOS带隙基准电压

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2017-11-01 DOI: 10.1109/ICAM.2017.8242166

Jun Zhao, Xiaohong Peng, Li-gang Hou, Yinan Zhang, Guoqing Sun

引用次数: 2

Research and design of add-based length-scalable dual-field modular multiplication-addition-subtraction 基于加的长度可伸缩双域模乘加减算法的研究与设计

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2017-11-01 DOI: 10.1109/ICAM.2017.8242136

Jiamin Li, Z. Dai, Wei Li, Suwen Yi, S. Zhou

{"title":"Research and design of add-based length-scalable dual-field modular multiplication-addition-subtraction","authors":"Jiamin Li, Z. Dai, Wei Li, Suwen Yi, S. Zhou","doi":"10.1109/ICAM.2017.8242136","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242136","url":null,"abstract":"Modular multiplication, addition, and subtraction being the core operation of Elliptic curve public(ECC) system, the decrease of area and the merging of structure have been a hot topic in recent years. This paper first analyzes the difference between multiplication type and addition type of modular multiplier. Then, Combined with the structural characteristics of the modular adder, and mixing modular adder and multiplier at both algorithm and structure level, this paper proposes an add-based length-scalable dual-field modular multiplication-addition-subtraction (ALDMAS), with a high resource reuse rate. The proposed ALDMAS with a 3-level pipeline accelerated structure can support dual-field multiplication and addition of any length within 576bits, therefore, it has a strong adaptability. Moreover this architecture, described by Verilog HDL, is integrated in CMOS 65nm technology library, with circuit maximum clock frequency being 487MHz (1.25∼3.5 times of the same type of modular multipliers), and the area being 36548 gates (only 0.23∼0.4 times of the related work).","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127313063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A high-sensitivity current-shunt monitor with extended input common-mode voltage range 具有扩展输入共模电压范围的高灵敏度电流分流监视器

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2017-11-01 DOI: 10.1109/ICAM.2017.8242129

Yaping Cheng, S. Huang, Jiaqi Yin, Q. Duan

引用次数: 1

Failure analysis on the low output power abnormity of a microsystem during the thermal cycle 热循环过程中微系统低输出功率异常故障分析

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2017-11-01 DOI: 10.1109/ICAM.2017.8242170

Jiajia Sun, Xu Wang, Zhibin Wang, Meng Meng, Zhimin Ding

引用次数: 0

Cooperative effort based wireless sensor network clustering algorithm for smart home application 基于协同努力的无线传感器网络聚类算法在智能家居中的应用

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2017-11-01 DOI: 10.1109/ICAM.2017.8242190

S. A. Imam, A. Choudhary, Aijaz M. Zaidi, M. Singh, V. Sachan

{"title":"Cooperative effort based wireless sensor network clustering algorithm for smart home application","authors":"S. A. Imam, A. Choudhary, Aijaz M. Zaidi, M. Singh, V. Sachan","doi":"10.1109/ICAM.2017.8242190","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242190","url":null,"abstract":"Present research work propose the design of a low energy and high throughput, hierarchical clustering based routing protocol for smart home sensor network application. Proposed protocol perform dynamic cluster head selection based on multiple node characteristics like node residual energy, node distance from sink and node average distance from neighbour nodes. Cluster head distribution is even and results in enhanced network lifetime. Sensor nodes process the sense data using local on-board processors and omit the redundant data from transmission. In this manner, cooperative effort by sensor nodes save significant amount of node transmission energy. Elongated lifetime and reduced data traffic in network reduce data loss rates during transmission and result in high throughput. Wireless channel model and path loss model for indoor residential environment are used for protocol simulation. Simulation is carried using MATLAB tool and results are obtained in terms of network lifetime, stability period, throughput etc. Results, as compared with existing protocols, proves the efficiency of proposed protocol.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"11 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130290833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

An innovative implementation of asynchronous for-loop circuit with click micropipeline 一种基于点击微流水线的异步闭环电路的创新实现

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2017-11-01 DOI: 10.1109/ICAM.2017.8242140

Huibo Guo, G. Feng, Anping He, Jinzhao Wu

引用次数: 1

Carrier frequency offset estimation and FPGA implementation in OFDM system OFDM系统中载波频偏估计及FPGA实现

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2017-11-01 DOI: 10.1109/ICAM.2017.8242186

L. Wei, Duan Peng

引用次数: 0

Power efficient all-digital delta-sigma TDC with differential gated delay line time integrator 功率高效的全数字δ - σ TDC与差分门控延迟线时间积分器

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2017-11-01 DOI: 10.1109/ICAM.2017.8242131

Parth Parekh, F. Yuan

{"title":"Power efficient all-digital delta-sigma TDC with differential gated delay line time integrator","authors":"Parth Parekh, F. Yuan","doi":"10.1109/ICAM.2017.8242131","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242131","url":null,"abstract":"This paper presents a low-power all-digital first-order single-bit delta-sigma time-to-digital converter (TDC) with a differential bi-directional gated delay line time integrator. The differential time integrator features low power consumption accredited to the use of only one bi-directional gated delay line in performing time integration, full compatibility with technology scaling, rapid time integration, and inherently digitized output. Differential time integration is obtained by employing a time bolun mapping a single-ended time variable to be integrated to a pair of differential time variable with an embedded constant time offset that satisfying minimum gating width constraint. The TDC was designed in an IBM 130 nm 1.2 V CMOS technology. A sinusoidal time input of 333 ps amplitude and 244 kHz frequency generated using a differential voltage-to-time converter (VTC) clocked at 33 MHz is digitized by the TDC. The TDC was analyzed using Spectre from Cadence Design Systems with BSIM4 device model. Simulation results demonstrate the TDC provides a SFDR of 41.8 dB, a SNDR of 37.7 dB, and a time resolution of 5.3 ps over frequency rang 109–488 kHz while consuming 0.9 mW.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132563774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A 318 nA quiescent current 0–10mA output transient enhanced low-dropout regulator applied in energy harvest system 318 nA静态电流0-10mA输出瞬态增强型低压差稳压器应用于能量采集系统

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2017-11-01 DOI: 10.1109/ICAM.2017.8242156

Hongguang Zhang, Zhangwen Tang

引用次数: 3

Small die area capacitive cross-coupled injection-locked frequency divider 小模面积电容交叉耦合注入锁定分频器

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2017-11-01 DOI: 10.1109/ICAM.2017.8242127

W. Lai, S. Jang, Meng-Yan Fang

引用次数: 1