用于合成和实现赛灵思FPGA器件的创新工具链

Yi Zuo, Anping He, Caihong Li, Lvying Yu
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引用次数: 0

摘要

综合和实现是硬件设计的两个基本步骤。该领域的大量工作综合并实现了从硬件描述语言(HDL)描述到目标FPGA设备的设计。我们介绍ISE +定制P&R,一个将Verilog设计转换为包含Xilinx FPGA实现模块的XDL的工具链。该工具链的一个关键方面是它既包含了商用FPGA设计套件的高效优化能力,又包含了实现开源第三方软件的灵活的底层控制能力。此外,该工具链可以自动生成定制的布局和布线,为大批量合成和实现异步FPGA设计提供了可行性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An innovation tool-chain for synthesis and implementation of Xilinx FPGA devices
Synthesis and implementation are two fundamental steps of the hardware design. Mountains of work in this area synthesize and implement your design from Hardware Description Language (HDL) description to the target FPGA device. We present ISE plus Customized P&R, a tool-chain converting Verilog designs into XDL that contains Xilinx FPGA implement modules. A key aspect of this tool-chain is that it both embraces the efficient optimal capacity of synthesizing commercial FPGA Design Suite and the flexible bottom control ability for the implementation of the open-source third-part software. Moreover, this tool-chain can automatically generate customized placement and routing, which provided a feasibility to synthesize and implement asynchronous FPGA designs in bulk without the manual labor.
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