一个12.42μA 0.192ppm/°C的高PSRR曲率补偿CMOS带隙基准电压

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2017-11-01 DOI:10.1109/ICAM.2017.8242166

Jun Zhao, Xiaohong Peng, Li-gang Hou, Yinan Zhang, Guoqing Sun

{"title":"一个12.42μA 0.192ppm/°C的高PSRR曲率补偿CMOS带隙基准电压","authors":"Jun Zhao, Xiaohong Peng, Li-gang Hou, Yinan Zhang, Guoqing Sun","doi":"10.1109/ICAM.2017.8242166","DOIUrl":null,"url":null,"abstract":"A high order curvature-compensated CMOS bandgap voltage reference(BGR) is presented in TSMC 0.35μm CMOS technology with low power low temperature-coefficient(TC) and high power supply rejection ratio(PSRR). The design is used in low dropout regulators which is applied in implanted chips. TC is compensated by adjusting resistor ratio which have different temperature characteristics. A PSRR enhance circuit is inserted in this circuit to maintain a constant gate-source voltage in the current mirror. A TC is 0.192ppm/°C at 3.3V supply and a line regulation is 4.5ppm/V at room temperature. The circuit has a constant voltage of 1.14 V. The circuit performs a PSRR property of 106dB@1kHz and 46dB@1MHz. The circuit consumes a maximum supply current of 12.42μA and start-up time is 2.04μs.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 12.42μA 0.192ppm/°C high PSRR curvature-compensated CMOS bandgap voltage reference\",\"authors\":\"Jun Zhao, Xiaohong Peng, Li-gang Hou, Yinan Zhang, Guoqing Sun\",\"doi\":\"10.1109/ICAM.2017.8242166\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high order curvature-compensated CMOS bandgap voltage reference(BGR) is presented in TSMC 0.35μm CMOS technology with low power low temperature-coefficient(TC) and high power supply rejection ratio(PSRR). The design is used in low dropout regulators which is applied in implanted chips. TC is compensated by adjusting resistor ratio which have different temperature characteristics. A PSRR enhance circuit is inserted in this circuit to maintain a constant gate-source voltage in the current mirror. A TC is 0.192ppm/°C at 3.3V supply and a line regulation is 4.5ppm/V at room temperature. The circuit has a constant voltage of 1.14 V. The circuit performs a PSRR property of 106dB@1kHz and 46dB@1MHz. The circuit consumes a maximum supply current of 12.42μA and start-up time is 2.04μs.\",\"PeriodicalId\":117801,\"journal\":{\"name\":\"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICAM.2017.8242166\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAM.2017.8242166","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

采用台积电0.35μm CMOS工艺，提出了一种低功耗、低温度系数(TC)和高电源抑制比(PSRR)的高阶曲率补偿CMOS带隙基准电压(BGR)。该设计用于植入芯片的低差稳压器。通过调节具有不同温度特性的电阻比来补偿热损耗。在该电路中插入PSRR增强电路，以保持电流镜中栅极源电压恒定。供电3.3V时的电压电压为0.192ppm/°C，室温时的电压电压为4.5ppm/V。该电路具有1.14 V的恒定电压。电路的PSRR性能为106dB@1kHz和46dB@1MHz。电路最大供电电流为12.42μA，启动时间为2.04μs。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 12.42μA 0.192ppm/°C high PSRR curvature-compensated CMOS bandgap voltage reference

A high order curvature-compensated CMOS bandgap voltage reference(BGR) is presented in TSMC 0.35μm CMOS technology with low power low temperature-coefficient(TC) and high power supply rejection ratio(PSRR). The design is used in low dropout regulators which is applied in implanted chips. TC is compensated by adjusting resistor ratio which have different temperature characteristics. A PSRR enhance circuit is inserted in this circuit to maintain a constant gate-source voltage in the current mirror. A TC is 0.192ppm/°C at 3.3V supply and a line regulation is 4.5ppm/V at room temperature. The circuit has a constant voltage of 1.14 V. The circuit performs a PSRR property of 106dB@1kHz and 46dB@1MHz. The circuit consumes a maximum supply current of 12.42μA and start-up time is 2.04μs.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)

自引率

0.00%

发文量