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2005 IEEE International SOI Conference Proceedings最新文献

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Novel ultra-low power RF lateral BJT on SOI-CMOS compatible substrate for SoC applications 新型超低功耗射频横向BJT在SoC应用的SOI-CMOS兼容衬底
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563561
I.-S.M. Sun, W. Ng, H. Mochizuki, K. Kanekiyo, T. Kobayashi, M. Toita, H. Imai, A. Ishikawa, S. Tamura, K. Takasuka
{"title":"Novel ultra-low power RF lateral BJT on SOI-CMOS compatible substrate for SoC applications","authors":"I.-S.M. Sun, W. Ng, H. Mochizuki, K. Kanekiyo, T. Kobayashi, M. Toita, H. Imai, A. Ishikawa, S. Tamura, K. Takasuka","doi":"10.1109/SOI.2005.1563561","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563561","url":null,"abstract":"This work presents an ultra-low power RF LBJT on SOI. The Johnson's product (f/sub /spl tau// /spl times/BV/sub CEO/) of the fabricated LBJTs ranges between 190-300 GHz-V. The f/sub max/ of the optimal device reaches 46 GHz at collector current density of only 0.15mA//spl mu/m/sup 2/. This LBJT is compatible with SOI-CMOS for SOI-BiCMOS integration, an ideal technology for RF and mixed-signal SoC.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131574077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Revised split C-V technique for mobility investigation in advanced devices 改进的分割C-V技术用于先进器械的移动性调查
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563555
V. Kilchytska, D. Lederer, P. Simon, N. Collaert, J. Raskin, D. Flandre
{"title":"Revised split C-V technique for mobility investigation in advanced devices","authors":"V. Kilchytska, D. Lederer, P. Simon, N. Collaert, J. Raskin, D. Flandre","doi":"10.1109/SOI.2005.1563555","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563555","url":null,"abstract":"In this paper we revise the split C-V technique widely used for mobility extraction. To extend its applicability we propose to use an integral of transconductance measured at high frequencies (HF) instead of the DC drain current. For the first time it is shown that such procedure allows not only to suppress parasitic gate-induced floating body effect (GIFBE), but also to improve the accuracy of mobility extraction in weak inversion (WI) regime. In this paper we apply our technique to partially-depleted (PD) SOI MOSFETs from a FinFET process and demonstrate its advantages in comparison to the standard method.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124200280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Considerations for single event effects in non-planar multi-gate SOI FETs 非平面多栅SOI场效应管中单事件效应的考虑
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563584
M. Alles, D. Ball, L. Massengill, peixiong zhao, K. Warren, R. Weller
{"title":"Considerations for single event effects in non-planar multi-gate SOI FETs","authors":"M. Alles, D. Ball, L. Massengill, peixiong zhao, K. Warren, R. Weller","doi":"10.1109/SOI.2005.1563584","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563584","url":null,"abstract":"Reductions in supply voltage and device dimensions, and increased transistor circuits in advanced circuits, make single event effects increasingly relevant. Non-planar multiple-gate FETs (MugFETs) are under consideration for /spl les/ 45 nm technology generations. In this work, we examine issues for SEE in advanced MugFETs using energy deposition and device simulations.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122076782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Ultra-low-power, high-performance, dynamic-threshold digital circuits in the FlexFET independently-double-gated SOI CMOS technology 采用FlexFET独立双门SOI CMOS技术的超低功耗、高性能动态阈值数字电路
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563542
D. Hackler, D. DeGregorio, S. Parke
{"title":"Ultra-low-power, high-performance, dynamic-threshold digital circuits in the FlexFET independently-double-gated SOI CMOS technology","authors":"D. Hackler, D. DeGregorio, S. Parke","doi":"10.1109/SOI.2005.1563542","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563542","url":null,"abstract":"This paper demonstrates IDG FlexFET CMOS in static CMOS ring oscillators, while the advantages of applying IDG-CMOS to dynamic domino CMOS logic circuits have recently been shown as well (H. Mahmoodi, 2004). IDG-CMOS has also recently been applied to several exciting new analog/MS/RF circuit applications, such as a single transistor mixer (L. Mathew, 2004).","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128380671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
150nm SOI embedded SRAMs with very low SER 150nm SOI嵌入式sram具有非常低的SER
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563583
D. Nelson, H. Liu, K. Golke, A. Kohli
{"title":"150nm SOI embedded SRAMs with very low SER","authors":"D. Nelson, H. Liu, K. Golke, A. Kohli","doi":"10.1109/SOI.2005.1563583","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563583","url":null,"abstract":"A split word line design technique that improves the soft error rate (SER) of high performance 150nm SOI embedded SRAMs is presented along with SER results.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129632675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Surface vs. bulk noise in SOI four-gate transistors SOI四栅极晶体管的表面与体噪声
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563574
K. Akarvardar, B. Dufrene, S. Cristoloveanu, J. Chroboczek, P. Gentil, B. Blalock, M. Mojarradi
{"title":"Surface vs. bulk noise in SOI four-gate transistors","authors":"K. Akarvardar, B. Dufrene, S. Cristoloveanu, J. Chroboczek, P. Gentil, B. Blalock, M. Mojarradi","doi":"10.1109/SOI.2005.1563574","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563574","url":null,"abstract":"Low-frequency noise characteristics of four-gate transistors (G/sup 4/-FETs) are presented distinguishing the surface conduction (MOSFET mode) and volume conduction (JFET mode). As the conducting channel moves from the surface to the bulk we observe that: (i) the noise level dramatically decreases; and (ii) the nature of the noise changes. The validity of the existing noise models for different conduction modes is discussed.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114462812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Oxidation induced stress effects on hole mobility as a function of transistor geometry in a 0.15 /spl mu/m dual gate oxide CMOS SOI process 在0.15 /spl mu/m双栅氧化CMOS SOI工艺中，氧化诱导应力对空穴迁移率的影响是晶体管几何形状的函数
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563575
P.S. Fechnerand, E. Vogt
{"title":"Oxidation induced stress effects on hole mobility as a function of transistor geometry in a 0.15 /spl mu/m dual gate oxide CMOS SOI process","authors":"P.S. Fechnerand, E. Vogt","doi":"10.1109/SOI.2005.1563575","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563575","url":null,"abstract":"Additional process complexity required for multiple gate oxide thicknesses has been demonstrated to cause significant impact on p-channel mobility through oxidation induced stress effects. This can occur even after the STI oxide planarization step. Therefore, process flow options to minimize all oxidations after island definition should be considered. The data presented here also underscores the need to understand and model the oxidation induced stress associated with the specific device of interest. Since these stresses have a major impact on device mobility and current drive, care must be taken to make sure variation in layout options such as stacking transistors in a single device island rather than individual islands do not lead to circuit design modeling errors sufficient to compromise circuit performance margins. SUPREM4 appears to be able to model this behavior but most circuit level transistor models are not capable of handling this level of detail or complexity.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123770513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
UV scanning for SOI defectivity monitoring 紫外扫描监测SOI缺陷
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563569
C. Moulin, D. Delprat, C. Maleville, W. Mcmillan, J. Payne, K. Bird well, R. Brun, R. Moirin
{"title":"UV scanning for SOI defectivity monitoring","authors":"C. Moulin, D. Delprat, C. Maleville, W. Mcmillan, J. Payne, K. Bird well, R. Brun, R. Moirin","doi":"10.1109/SOI.2005.1563569","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563569","url":null,"abstract":"This paper shows how a new generation of inspection system enables us to monitor SOI as requested in the ITRS roadmaps; it shows also the large amount of key information we can collect, giving us important feedback on the SOI process.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116542029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Circuit to measure high speed pulse I-V characteristics with only DC I/O's 仅用直流I/O测量高速脉冲I- v特性的电路
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563540
M. Ketchen, M. Bhushan, K. Jenkins
{"title":"Circuit to measure high speed pulse I-V characteristics with only DC I/O's","authors":"M. Ketchen, M. Bhushan, K. Jenkins","doi":"10.1109/SOI.2005.1563540","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563540","url":null,"abstract":"We have implemented a new approach for measuring the pulse I-V characteristics of a set of nominally identical MOSFETs. In this scheme, all high speed signals are contained entirely inside the test structure itself. Only DC inputs and outputs are required for direct measurement of both DC and AC I-V characteristics at frequencies up to the GHz range.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129959485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new dose rate model for SOI MOSFETs and its implementation in SPICE SOI mosfet的新剂量率模型及其在SPICE中的实现
2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI: 10.1109/SOI.2005.1563556
H. Liu, K. Golke, S.T. Liu
{"title":"A new dose rate model for SOI MOSFETs and its implementation in SPICE","authors":"H. Liu, K. Golke, S.T. Liu","doi":"10.1109/SOI.2005.1563556","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563556","url":null,"abstract":"A new SPICE based dose rate model is proposed for SOI MOSFETs, which accounts for collections of excess carriers by both source/body and drain/body junctions. It is also identified that the parasitic bipolar transistor does not play a significant role within the range of dose rate of interest. An implementation method for circuit level simulation is described. The validity of this model has been verified by test results.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134237199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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