2020 IEEE 33rd International System-on-Chip Conference (SOCC)最新文献_第3页

Holistic 2.5D Chiplet Design Flow: A 65nm Shared-Block Microcontroller Case Study 整体2.5D芯片设计流程:65nm共享块微控制器案例研究

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524798

M. Kabir, Yarui Peng

{"title":"Holistic 2.5D Chiplet Design Flow: A 65nm Shared-Block Microcontroller Case Study","authors":"M. Kabir, Yarui Peng","doi":"10.1109/socc49529.2020.9524798","DOIUrl":"https://doi.org/10.1109/socc49529.2020.9524798","url":null,"abstract":"Traditionally, different components of a system are integrated through Printed Circuit Boards (PCB). The long traces on PCB have severe power loss and limit the bandwidth of the interconnects between the components. Advanced packaging offers high-bandwidth, low power, and high-performance inter-die communications with compact sizes and dense pin arrays. 2.5D integration further provides better thermal dissipation, lower cost, and higher yield compared to 3D stacking. Novel CAD tool flows dedicated to 2.5D chiplet designs are essential to enable flexible and efficient 2.5D system designs. In this paper, we present our design, optimization, and analysis methodologies and a design case study implementing an ARM Cortex-M0 microcontroller system using a holistic 2.5D tool flow. We use TSMC 65nm as our chiplet implementation technology with a modified metal stack referring to 2.5D Fan-Out Wafer-Level Packaging (FOWLP) solutions. We also discuss design techniques for chiplet reuse and the Drop-in design approach to develop low-power, low-cost, and high-performance flavors of a 2.5D system. We compare the 2.5D system with its 2D counterpart to validate the holistic design flow.","PeriodicalId":114740,"journal":{"name":"2020 IEEE 33rd International System-on-Chip Conference (SOCC)","volume":"46 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130318142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A SpaceWire PHY with Double Data Rate and Fallback Redundancy 具有双数据速率和回退冗余的SpaceWire PHY

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524763

Mong Tee Sim, Yanyan Zhuang

引用次数: 1

Improving the Performance of a NoC-based CNN Accelerator with Gather Support 利用Gather支持改进基于noc的CNN加速器的性能

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524799

Binayak Tiwari, Mei Yang, Xiaohang Wang, Yingtao Jiang, V. Muthukumar

引用次数: 1

C2IM: A Compact Computing-In-Memory Unit of 10 Transistors with Standard 6T SRAM C2IM:采用标准6T SRAM的10个晶体管的紧凑型内存计算单元

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524791

Erxiang Ren, Li Luo, Zheyu Liu, F. Qiao, Qi Wei

引用次数: 0

2020 Additional Reviewers 2020新增审稿人

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524721

引用次数: 0

Programmable Voltage Reference Circuit Using an Analog Floating Gate Device 采用模拟浮门器件的可编程参考电压电路

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524788

S. Nimmalapudi, H. Stiegler, A. Marshall, Keith Jarreau

引用次数: 2

2020 Steering Committee 2020年指导委员会

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524724

引用次数: 0

A Low-Cost Fault Injection Attack Resilient FSM Design 一种低成本故障注入攻击弹性FSM设计

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524779

Ziming Wang, Aijiao Cui, G. Qu

{"title":"A Low-Cost Fault Injection Attack Resilient FSM Design","authors":"Ziming Wang, Aijiao Cui, G. Qu","doi":"10.1109/socc49529.2020.9524779","DOIUrl":"https://doi.org/10.1109/socc49529.2020.9524779","url":null,"abstract":"Finite state machine (FSM) plays an important role in digital circuit design. Since it stores the system states and controls system functionality, security vulnerabilities of FSM have been exploited extensively. Among the potential attacks, fault inject attack (FIA) is one of the most severe and most challenging to defend against. Unlike existing countermeasures, we propose a novel structure for FSM state flip flop design that can mitigate any kind of timing based FIAs. Our key idea is to sample the flip flop input signals multiple times during one clock cycle, and then compare these values to determine the correct one. This can effectively defeat all the FIAs based on violating FSM state setup time constraint. In addition, such design will make the design more robust against jitters. In order to reduce the design overhead, we use the low-cost transmission gates to implement the proposed latch and flip flop. We use Hspice to simulate the error conditions with delayed input data and jitter and the results confirm that our design is error resilient. We also implement the FSM in AES with our proposed flip flops and compare the area overhead with existing FIA countermeasures. Results show that the two state-of-the-art approaches have 2X and 4X area overhead than ours.","PeriodicalId":114740,"journal":{"name":"2020 IEEE 33rd International System-on-Chip Conference (SOCC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122546798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Exploring the Scalability of OpenCL Coarse Grained Parallelism on Cloud FPGAs 探讨OpenCL粗粒度并行在云fpga上的可扩展性

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524765

Jhanani Thiagarajan, Arnab A. Purkayastha, A. Patil, H. Tabkhi

{"title":"Exploring the Scalability of OpenCL Coarse Grained Parallelism on Cloud FPGAs","authors":"Jhanani Thiagarajan, Arnab A. Purkayastha, A. Patil, H. Tabkhi","doi":"10.1109/socc49529.2020.9524765","DOIUrl":"https://doi.org/10.1109/socc49529.2020.9524765","url":null,"abstract":"OpenCL programming ability combined with FPGAs pipelined parallelism have enabled high-performance execution and power-efficient solutions for massively parallel applications. This paper provides an exhaustive study on the scalability of OpenCL coarse-grain parallelism, Compute Unit (CU) replication on cloud FPGAs. This work demonstrates that for many applications there is an optimum number of CUs to achieve the maximum performance benefits with respect to memory bandwidth, memory conflicts introduced by CU replication and available FPGA resources. At the same time, the paper provides a source-code template and an optimized front-end design tool to explore and identify the optimum CU number for a given application, while hiding the programming and exploration difficulties from programmers. Our experimental results on 15 applications taken from the Xilinx SDAccel v2017.4 suite and the Rodinia Benchmark Suite v3.1 show a speedup of 6.2X, bandwidth improvement of 3.5X with a mere 1.04X power and less than 10% resource utilization on average. In addition, our tool results in a 31% improvement in the total design synthesis time for an illustrative Histogram application.","PeriodicalId":114740,"journal":{"name":"2020 IEEE 33rd International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128478204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Energy-Efficient Adiabatic Circuits Using Transistor-Level Monolithic 3D Integration

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524748

Ivan Miketic, E. Salman

{"title":"Energy-Efficient Adiabatic Circuits Using Transistor-Level Monolithic 3D Integration","authors":"Ivan Miketic, E. Salman","doi":"10.1109/socc49529.2020.9524748","DOIUrl":"https://doi.org/10.1109/socc49529.2020.9524748","url":null,"abstract":"Charge-recycling adiabatic circuits are recently receiving increased attention due to both high energy-efficiency and higher resistance against side-channel attacks. These characteristics make adiabatic circuits a promising technique for Internet-of-things based applications. One of the important limitations of adiabatic logic is the higher intra-cell interconnect capacitance due to differential outputs and cross-coupled pMOS transistors. Since energy consumption has quadratic dependence on capacitance in adiabatic circuits (unlike conventional static CMOS where dependence is linear), higher interconnect capacitance significantly degrades the overall power savings that can be achieved by adiabatic logic, particularly in nanoscale technologies. In this paper, monolithic 3D integrated adiabatic circuits are introduced where transistor-level monolithic 3D technology is used to implement adiabatic gates. A 45 nm two-tier Mono3D PDK is used to demonstrate the proposed approach. Monolithic inter-tier vias are leveraged to significantly reduce parasitic interconnect capacitance, achieving up to 47% reduction in power-delay product as compared to 2D adiabatic circuits in a 45 nm technology node.","PeriodicalId":114740,"journal":{"name":"2020 IEEE 33rd International System-on-Chip Conference (SOCC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127849702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0