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2016 31st Symposium on Microelectronics Technology and Devices (SBMicro)最新文献

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n-Channel bulk and DTMOS FinFETs: Investigation of GIDL and gate leakage currents n沟道体和DTMOS finfet: GIDL和栅极泄漏电流的研究
2016 31st Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 1900-01-01 DOI: 10.1109/SBMICRO.2016.7731350
Caio Malingre Magan, J. Martino, E. Simoen, C. Claeys, M. G. Cano de Andrade
{"title":"n-Channel bulk and DTMOS FinFETs: Investigation of GIDL and gate leakage currents","authors":"Caio Malingre Magan, J. Martino, E. Simoen, C. Claeys, M. G. Cano de Andrade","doi":"10.1109/SBMICRO.2016.7731350","DOIUrl":"https://doi.org/10.1109/SBMICRO.2016.7731350","url":null,"abstract":"In this work GIDL (Gate Induced Drain Leakage) and Gate Leakage Currents (Ig) have been experimentally investigated for different dimensions of Bulk FinFETs with and without Dynamic Threshold MOS configuration (DTMOS) in linear and saturation regions. The results indicate that Bulk FinFETs present lower gate leakage currents than DTMOS FinFETs. In addition, an opposite IG behavior of those devices was observed when the channel lengths change. On the other hand, for long channels FinFETs the GIDL effect is lower in devices with DTMOS configuration because the benefit of DTMOS operation becomes higher.","PeriodicalId":113603,"journal":{"name":"2016 31st Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"275 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126332467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Influence of different UTBB SOI technologies on analog parameters 不同UTBB SOI技术对模拟参数的影响
2016 31st Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 1900-01-01 DOI: 10.1109/SBMICRO.2016.7731356
V. Itocazu, V. Sonnenberg, E. Simoen, C. Claeys, J. Martino
{"title":"Influence of different UTBB SOI technologies on analog parameters","authors":"V. Itocazu, V. Sonnenberg, E. Simoen, C. Claeys, J. Martino","doi":"10.1109/SBMICRO.2016.7731356","DOIUrl":"https://doi.org/10.1109/SBMICRO.2016.7731356","url":null,"abstract":"This paper presents an analysis of the influence of the silicon film thickness and the gate dielectric material on analog parameters in Ultra Thin Body and Buried Oxide (UTBB) SOl nMOSFET devices with and without Ground Plane (GP) for two different channel lengths (1μm and 70nm). The analysis is based on experimental data and simulations results. The presence of a GP improves the transconductance in the saturation region due to the strong coupling between front and back gates, but only in devices with thinner silicon film and L = 1μm. Devices with short channel length (70nm) have a strong influence of drain electrical field penetration, improving the analog parameters in devices without Ground Plane. The same effect occurs in devices with a thicker silicon film. Devices with high-κ material as gate dielectric present less influence of the presence of a Ground Plane.","PeriodicalId":113603,"journal":{"name":"2016 31st Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132407750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Ground plane influence on zero-temperature-coefficient in SOI UTBB MOSFETs with different silicon film thicknesses 地平面对不同硅膜厚度SOI UTBB mosfet零温度系数的影响
2016 31st Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 1900-01-01 DOI: 10.1109/SBMICRO.2016.7731326
C. Macambira, V. Itocazu, L. Almeida, J. Martino, E. Simoen, C. Claeys
{"title":"Ground plane influence on zero-temperature-coefficient in SOI UTBB MOSFETs with different silicon film thicknesses","authors":"C. Macambira, V. Itocazu, L. Almeida, J. Martino, E. Simoen, C. Claeys","doi":"10.1109/SBMICRO.2016.7731326","DOIUrl":"https://doi.org/10.1109/SBMICRO.2016.7731326","url":null,"abstract":"This paper presents an analysis of the Ground Plane (GP) influence on the Zero Temperature Coefficient (ZTC) in Ultra Thin Body and Buried Oxide (UTBB) Silicon On Insulator (SOI) nMOS transistors for different silicon thicknesses (tSi) based on experimental data and analytical models. The presence of a GP increases the values of the bias voltage of ZTC (VZTC) due to the reduction of the substrate effects in the device and consequently the increase of threshold voltage. The VZTC shows to be inversely proportional to the silicon thickness. All results are confirmed by the analytical model for the threshold voltage, which is the predominant factor in the ZTC point for this technology, both showing the same tendency.","PeriodicalId":113603,"journal":{"name":"2016 31st Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114301846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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