V. Itocazu, V. Sonnenberg, E. Simoen, C. Claeys, J. Martino
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引用次数: 4
摘要
本文分析了两种不同通道长度(1μm和70nm)下，硅膜厚度和栅极介质材料对超薄体和埋地氧化物(UTBB) SOl nMOSFET器件模拟参数的影响。分析基于实验数据和仿真结果。由于前后栅极之间的强耦合，GP的存在改善了饱和区域的跨导，但仅适用于硅膜较薄且L = 1μm的器件。短通道长度(70nm)的器件对漏极电场穿透的影响较大，改善了无接地面器件的模拟参数。同样的效果也发生在硅膜较厚的器件上。采用高-κ材料作为栅极介质的器件受接地面的影响较小。
Influence of different UTBB SOI technologies on analog parameters
This paper presents an analysis of the influence of the silicon film thickness and the gate dielectric material on analog parameters in Ultra Thin Body and Buried Oxide (UTBB) SOl nMOSFET devices with and without Ground Plane (GP) for two different channel lengths (1μm and 70nm). The analysis is based on experimental data and simulations results. The presence of a GP improves the transconductance in the saturation region due to the strong coupling between front and back gates, but only in devices with thinner silicon film and L = 1μm. Devices with short channel length (70nm) have a strong influence of drain electrical field penetration, improving the analog parameters in devices without Ground Plane. The same effect occurs in devices with a thicker silicon film. Devices with high-κ material as gate dielectric present less influence of the presence of a Ground Plane.
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