发布求助
文献互助 智能选刊 最新文献

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)最新文献

筛选
英文 中文
Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations 并联电场隧道场效应管的性能限制及改进栅极和沟道结构的改进
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818815
Y. Morita, T. Mori, S. Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, T. Matsukawa, K. Endo, S. O'Uchi, Yongxun Liu, M. Masahara, H. Ota
{"title":"Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations","authors":"Y. Morita, T. Mori, S. Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, T. Matsukawa, K. Endo, S. O'Uchi, Yongxun Liu, M. Masahara, H. Ota","doi":"10.1109/ESSDERC.2013.6818815","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818815","url":null,"abstract":"The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field, was evaluated. The TFET was fabricated by inserting a parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit of the drain current caused by the self-voltage-drop effect in the ultrathin channel layer. We also propose a scheme to improve the performance of the TFETs by modification of the gate and channel configurations.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"61 4-5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133017943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Investigation of SRAM using BTI-aware statistical compact models 基于bti感知统计紧凑模型的SRAM研究
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818850
J. Ding, D. Reid, C. Millar, A. Asenov
{"title":"Investigation of SRAM using BTI-aware statistical compact models","authors":"J. Ding, D. Reid, C. Millar, A. Asenov","doi":"10.1109/ESSDERC.2013.6818850","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818850","url":null,"abstract":"In this paper, statistical variability and different levels of BTI degradation are introduced into a compact model by statistical parameter extraction. Static Random Access Memory (SRAM) is used to test the compact model and to investigate the effects of MOSFET statistical variability and degradation at circuit level. Statistical distributions of Static Noise Margin (SNM) under different scenarios representing various degradation levels as well as mismatch levels between `on' and the rest of the SRAM cell transistors are compared to investigate their impacts on SRAM stability. A surface response model of the dependence of the mean and standard deviation of SNM on circuit ageing and transient stress is also developed to quickly evaluate SRAM stability at arbitrary degradation levels.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131058697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The Coupled Atom Transistor: A first realization with shallow donors implanted in a FDSOI silicon nanowire 耦合原子晶体管:首次实现将浅供体植入FDSOI硅纳米线
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818840
B. Voisin, B. Roche, E. Dupont-Ferrier, B. Sklénard, M. Cobian, X. Jehl, O. Cueto, R. Wacquez, M. Vinet, Y. Niquet, S. D. Franceschi, M. Sanquer
{"title":"The Coupled Atom Transistor: A first realization with shallow donors implanted in a FDSOI silicon nanowire","authors":"B. Voisin, B. Roche, E. Dupont-Ferrier, B. Sklénard, M. Cobian, X. Jehl, O. Cueto, R. Wacquez, M. Vinet, Y. Niquet, S. D. Franceschi, M. Sanquer","doi":"10.1109/ESSDERC.2013.6818840","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818840","url":null,"abstract":"Following the recent development of Single Atom Transistors [1,2], we realized the first Coupled Atom Transistor in a small silicon nanowire MOSFET. Three independent gates control two donors connected in series between the source and the drain in a small volume of silicon. The devices, either implanted with Phosphorus (1024m-3) or Arsenic atoms, are fabricated with SOI technology on 200 and 300 mm wafers [3]. We observe resonant transport through two donors in series, and spectroscopy of a single donor state can be performed. We further demonstrate charge pumping and coherent electron exchange between the two donors involving Landau-Zener transitions.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117234851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Atomistic simulation of electron and phonon transport in nano-devices 纳米器件中电子和声子输运的原子模拟
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818880
M. Luisier, R. Rhyner
{"title":"Atomistic simulation of electron and phonon transport in nano-devices","authors":"M. Luisier, R. Rhyner","doi":"10.1109/ESSDERC.2013.6818880","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818880","url":null,"abstract":"In this paper, the electrical, thermal, and coupled electro-thermal properties of silicon nanowire field-effect transistors (NWFETs) are investigated through advanced numerical simulations. An atomistic quantum transport solver based on the Non-equilibrium Green's Function (NEGF) formalism is utilized as modeling tool. The electron characteristics are treated within an empirical tight-binding basis, while a modified valence-force-field method is used to describe phonons. Device simulations going beyond the ballistic limit of transport are performed: electron-phonon interactions with an equilibrium and out-of-equilibrium phonon population are considered as well as an-harmonic phonon-phonon scattering. It is found that ultrascaled Si NWFETs with a gate length of 15 nm operate at about 50% of their ballistic limit. This poor performance can be explained by large self-heating effects that drastically increase the lattice temperature and thus reduce the drain current.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129058744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
2D electronics: Graphene and beyond 二维电子学:石墨烯及其他
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818814
W. Cao, Jiahao Kang, W. Liu, Yasin Khatami, D. Sarkar, K. Banerjee
{"title":"2D electronics: Graphene and beyond","authors":"W. Cao, Jiahao Kang, W. Liu, Yasin Khatami, D. Sarkar, K. Banerjee","doi":"10.1109/ESSDERC.2013.6818814","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818814","url":null,"abstract":"In this paper, we review the essential physics that lead to the most impressive properties of two-dimensional (2D) nanocrystals, primarily graphene and transition-metal dichalcogenides (TMD). We also highlight some applications uniquely enabled by these 2D materials in the nanoelectronics domain and discuss the related challenges and opportunities.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131945455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
MEMS for automotive and consumer electronics 用于汽车和消费电子产品的MEMS
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818809
S. Finkbeiner
{"title":"MEMS for automotive and consumer electronics","authors":"S. Finkbeiner","doi":"10.1109/ESSDERC.2013.6818809","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818809","url":null,"abstract":"Micro-Electro-Mechanical Systems (MEMS) are sensing the environmental conditions and give input to electronic control systems. MEMS are miniature systems which usually combine tiny mechanical structures with electronic circuits. Typical MEMS structures have a size of a few micrometers. MEMS sensors make system reactions to human needs more intelligent, precise, and at much faster reaction rates than humanly possible. Today MEMS sensors can be found in nearly every motor vehicle, smart phone or laptop. Due to continuous product innovations, the sensors find their way into more and more applications in automotive and consumer electronics. According to IHS iSuppli an amount of 4.3 billion micromechanical sensors were sold in 2011 with an impressive increase to 9.8 billion sensors in 2015 - a growth rate of 23% per year. These growth rates are only possible with continuous efforts to improve the performance and to decrease the size, power consumption and costs of the sensors. Historically, these improvements have lead to the breakthrough to industrial mass production for MEMS. This was achieved over the last 20 years by intense and successful development activities combined with the experience of volume production of billions of sensors. Since then, MEMS technology has enabled accelerometers, gyroscopes, geomagnetic sensors, barometric pressure sensors, inkjet nozzles or micro-mirrors for Digital-Light Processing (DLP) projection systems. Driving future applications in consumer electronics will be Human-Machine Interfaces (HMI), Augmented Reality (AR) and in-door navigation.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130232269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 93
Ultrahigh-voltage SiC devices for future power infrastructure 未来电力基础设施的超高压SiC器件
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818812
T. Kimoto
{"title":"Ultrahigh-voltage SiC devices for future power infrastructure","authors":"T. Kimoto","doi":"10.1109/ESSDERC.2013.6818812","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818812","url":null,"abstract":"Silicon carbide (SiC) is a newly-emerging wide bandgap semiconductor, by which high-voltage, low-loss power devices can be realized owing to its superior properties. This paper reviews recent progress in SiC material and device technologies for power device applications. Benefits and remaining issues of ultrahigh-voltage SiC power devices are highlighted. Through progress in fast epitaxy and defect reduction technologies, high-purity (~1014 cm-3) and thick (> 100 μm) SiC epilayers with long carrier lifetimes (> 30 μs) can be employed for fabrication of ultrahigh-voltage devices. By utilizing such epilayers and appropriate junction termination structures, ultrahigh-voltage blocking over 20 kV has been achieved in SiC PiN diodes and transistors.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130437212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Multi-scale computational framework for the evaluation of variability in the programing window of a flash cell with molecular storage 具有分子存储的闪存电池编程窗口可变性评估的多尺度计算框架
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818861
V. Georgiev, S. Markov, Laia Vilà‐Nadal, Cristoph Busche, L. Cronin, A. Asenov
{"title":"Multi-scale computational framework for the evaluation of variability in the programing window of a flash cell with molecular storage","authors":"V. Georgiev, S. Markov, Laia Vilà‐Nadal, Cristoph Busche, L. Cronin, A. Asenov","doi":"10.1109/ESSDERC.2013.6818861","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818861","url":null,"abstract":"We report a modeling study of a conceptual non-volatile memory cell based on inorganic molecular clusters as a storage media embedded in the gate dielectric of a MOSFET. For the purpose of this study we have developed a multi-scale simulation framework that enables the evaluation of the variability in the programming window of a flash-cell with sub-20nm gate length. Furthermore, we have studied the threshold voltage statistical variability due to the presence of random dopant fluctuations and polyoxometalate (POM) distribution in the cell. The simulation framework and the general conclusions of our work are transferrable to flash cells based on alternative molecules used for a storage media.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125837820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Micron-scale inkjet-assisted digital lithography for large-area flexible electronics 用于大面积柔性电子器件的微米尺度喷墨辅助数字光刻技术
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 1900-01-01 DOI: 10.1109/ESSDERC.2013.6818873
R. Sporea, A. Alshammari, S. Georgakopoulos, J. Underwood, M. Shkunov, S. Silva
{"title":"Micron-scale inkjet-assisted digital lithography for large-area flexible electronics","authors":"R. Sporea, A. Alshammari, S. Georgakopoulos, J. Underwood, M. Shkunov, S. Silva","doi":"10.1109/ESSDERC.2013.6818873","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818873","url":null,"abstract":"Large-area electronics require cost-effective yet precise patterning of electrodes. We demonstrate a simple electrode patterning technique capable of micron-scale gap formation, that allows the patterning of a larger variety of metals than the current portfolio of jettable metallic ink comprises and does not require a high-temperature sintering step. However, this method can produce large variations in gap size resulting in inconsistent and irreproducible transistor drain current. We propose that source-gated transistors (SGTs) are well suited to this technique, as they have a saturated drain current independent of source-drain separation, thus leading to improved current uniformity despite inconsistencies in gap size.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134510973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
ACE: A robust variability and aging sensor for high-k/metal gate SoC ACE:用于高k/金属栅极SoC的鲁棒变异性和老化传感器
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 1900-01-01 DOI: 10.1109/ESSDERC.2013.6818849
Min Chen, V. Reddy, S. Krishnan, J. Ondrusek, Yu Cao
{"title":"ACE: A robust variability and aging sensor for high-k/metal gate SoC","authors":"Min Chen, V. Reddy, S. Krishnan, J. Ondrusek, Yu Cao","doi":"10.1109/ESSDERC.2013.6818849","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818849","url":null,"abstract":"A novel on-chip variability and aging sensor has been designed for robust generation of a voltage guard band in high-K/metal gate technologies. It is the first single sensor solution that is capable of guard-banding for both NBTI and PBTI effects. It offers the SoC the capability to dynamically adjust the on-chip guard-band for joint power-reliability optimization.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115059651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书