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2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)最新文献

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High-ohmic resistors using nanometer-thin pure-boron chemical-vapour-deposited layers 采用纳米薄纯硼化学气相沉积层的高欧姆电阻
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 1900-01-01 DOI: 10.1109/ESSDERC.2013.6818856
N. Golshani, V. Mohammadi, S. Ramesh, L. Nanver
{"title":"High-ohmic resistors using nanometer-thin pure-boron chemical-vapour-deposited layers","authors":"N. Golshani, V. Mohammadi, S. Ramesh, L. Nanver","doi":"10.1109/ESSDERC.2013.6818856","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818856","url":null,"abstract":"Integrated resistors are fabricated by using pure boron (PureB) depositions to create a p-type conductive layer on n-type silicon. Sheet resistance values in the 100 kΩ/□ range are reliably and reproducibly realized. The resistors made in this material are linear and display low temperature coefficients of a few hundred ppm/°C and good tolerances.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115535273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Complementary n- and p-type TFETs on the same InAs/Al0.05Ga0.95Sb platform 在相同InAs/Al0.05Ga0.95Sb平台上互补的n型和p型tfet
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 1900-01-01 DOI: 10.1109/ESSDERC.2013.6818821
E. Baravelli, E. Gnani, R. Grassi, A. Gnudi, S. Reggiani, G. Baccarani
{"title":"Complementary n- and p-type TFETs on the same InAs/Al0.05Ga0.95Sb platform","authors":"E. Baravelli, E. Gnani, R. Grassi, A. Gnudi, S. Reggiani, G. Baccarani","doi":"10.1109/ESSDERC.2013.6818821","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818821","url":null,"abstract":"Design of complementary n- and p-type heterojunction tunnel field-effect transistors (TFETs) realized with the same InAs/Al0.05Ga0.95Sb material pair is carried out in this work using 3D, full-quantum simulations. Several design parameters are optimized, leading to a TFET pair with similar dimensions and feasible aspect ratios, which exhibit average subthreshold slopes around 30 mV/dec and relatively high on-currents of 280 (n-TFET) and 165 μA/ μm (p-TFET) at 0.4 V supply voltage. This is combined with low operating power (LOP) compatible off-currents, which makes the proposed technology platform well suited for LOP applications and even usable in HP scenarios. Devices with reduced cross section (7 nm instead of 10 nm) are also proposed as good candidates for low standby power (LSTP) scenarios.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131833443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Compact modeling of STT-MTJ for SPICE simulation 面向SPICE仿真的STT-MTJ紧凑建模
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 1900-01-01 DOI: 10.1109/ESSDERC.2013.6818887
Zihan Xu, K. Sutaria, Chengen Yang, C. Chakrabarti, Yu Cao
{"title":"Compact modeling of STT-MTJ for SPICE simulation","authors":"Zihan Xu, K. Sutaria, Chengen Yang, C. Chakrabarti, Yu Cao","doi":"10.1109/ESSDERC.2013.6818887","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818887","url":null,"abstract":"STT-MTJ is a promising device for future high-density and low-power integrated systems. To enable design exploration of STT-MTJ, this paper presents a fully compact model for efficient SPICE simulation. Derived from the fundamental LLG equation, the new model consists of RC elements that are closed-form solutions of device geometry and material properties. They support transient SPICE simulations, providing necessary details beyond the macromodel. The accuracy is validated with numerical results and published data.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134039798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process STI和eSiGe源/漏外延诱发应力模型在28纳米技术与替代栅极(RMG)工艺
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 1900-01-01 DOI: 10.1109/ESSDERC.2013.6818843
D. Jang, M. Bardon, D. Yakimets, K. Miyaguchi, A. D. Keersgieter, T. Chiarella, R. Ritzenthaler, M. Dehan, A. Mercha
{"title":"STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process","authors":"D. Jang, M. Bardon, D. Yakimets, K. Miyaguchi, A. D. Keersgieter, T. Chiarella, R. Ritzenthaler, M. Dehan, A. Mercha","doi":"10.1109/ESSDERC.2013.6818843","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818843","url":null,"abstract":"As CMOS technology goes into the nanoscale regime, the impact of layout on the device performance becomes increasingly important. In this paper, we propose a physics-based analytical model for Layout Dependent Effects (LDE) due to shallow trench isolation (STI) stress in 28 nm technology using “gate-last” process (Replacement Gate - RMG). The impact of active size and active width are considered and the model links between stress and device parameters such as the mobility and threshold voltage. The model is validated with experimental data. In addition, we investigate the impact of embedded Silicon-Germanium source/drain (eSiGe S/D) stressors in PMOS. Stronger mobility degradation is predicted for small width devices once eSiGe S/D is used. It results in a larger drop of normalized current (μA/μm) (-16%) once compared to transistors without eSiGe (-7%).","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124002657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
DC and small-signal numerical simulation of graphene base transistor for terahertz operation 石墨烯基晶体管太赫兹工作的直流和小信号数值模拟
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 1900-01-01 DOI: 10.1109/ESSDERC.2013.6818881
V. D. Lecce, R. Grassi, A. Gnudi, E. Gnani, S. Reggiani, G. Baccarani
{"title":"DC and small-signal numerical simulation of graphene base transistor for terahertz operation","authors":"V. D. Lecce, R. Grassi, A. Gnudi, E. Gnani, S. Reggiani, G. Baccarani","doi":"10.1109/ESSDERC.2013.6818881","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818881","url":null,"abstract":"The working principles of the hot-electron graphene base transistor (GBT) for analog terahertz operation have been investigated by means of a self-consistent Schrodinger-Polsson solver code. Its regions of operation are defined and discussed. With the help of a small-signal model, it is shown that the cutoff frequency does not depend on the quantum capacitance of the graphene layer, which on the contrary severely affects the intrinsic voltage gain, and that terahertz operation is possible.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132279741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors Al2O3位置对高k金属门控DRAM外围晶体管性能和可靠性的影响
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 1900-01-01 DOI: 10.1109/ESSDERC.2013.6818851
M. Aoulaiche, E. Simoen, R. Ritzenthaler, T. Schram, H. Arimura, M. Cho, T. Kauerauf, G. Groeseneken, N. Horiguchi, A. Thean, A. Federico, F. Crupi, A. Spessot, C. Caillat, P. Fazan, H.-J. Na, Y. Son, K. B. Noh
{"title":"Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors","authors":"M. Aoulaiche, E. Simoen, R. Ritzenthaler, T. Schram, H. Arimura, M. Cho, T. Kauerauf, G. Groeseneken, N. Horiguchi, A. Thean, A. Federico, F. Crupi, A. Spessot, C. Caillat, P. Fazan, H.-J. Na, Y. Son, K. B. Noh","doi":"10.1109/ESSDERC.2013.6818851","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818851","url":null,"abstract":"The impact of the Al<sub>2</sub>O<sub>3</sub> position with respect to HfO<sub>2</sub> in the process flow, is investigated. It is shown that Al<sub>2</sub>O<sub>3</sub> incorporation in order to increase the pMOS threshold voltage, slightly degrades the mobility, slightly increases NBTI and increases the EOT with respect to the reference without Al<sub>2</sub>O<sub>3</sub> Moreover, the trap density profiles depend on the Al<sub>2</sub>O<sub>3</sub> position: higher in the interfacial layer when Al<sub>2</sub>O<sub>3</sub> is below and higher in the HfO<sub>2</sub> when Al<sub>2</sub>O<sub>3</sub> is above HfO<sub>2</sub>. Furthermore, Al<sub>2</sub>O<sub>3</sub> below HfO<sub>2</sub> shows higher gate leakage, reduced LF noise but marginal NBTI difference compared to AL<sub>2</sub>O<sub>3</sub> above HfO<sub>2</sub>.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124706597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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