Y. Morita, T. Mori, S. Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, T. Matsukawa, K. Endo, S. O'Uchi, Yongxun Liu, M. Masahara, H. Ota
{"title":"Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations","authors":"Y. Morita, T. Mori, S. Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, T. Matsukawa, K. Endo, S. O'Uchi, Yongxun Liu, M. Masahara, H. Ota","doi":"10.1109/ESSDERC.2013.6818815","DOIUrl":null,"url":null,"abstract":"The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field, was evaluated. The TFET was fabricated by inserting a parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit of the drain current caused by the self-voltage-drop effect in the ultrathin channel layer. We also propose a scheme to improve the performance of the TFETs by modification of the gate and channel configurations.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"61 4-5","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2013.6818815","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field, was evaluated. The TFET was fabricated by inserting a parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit of the drain current caused by the self-voltage-drop effect in the ultrathin channel layer. We also propose a scheme to improve the performance of the TFETs by modification of the gate and channel configurations.