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An experimental study of integrated DMOS transistors with increased energy capability 提高能量容量的集成DMOS晶体管的实验研究
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818827
T. Zawischka, M. Pfost, Michael Ebli, D. Costachescu
{"title":"An experimental study of integrated DMOS transistors with increased energy capability","authors":"T. Zawischka, M. Pfost, Michael Ebli, D. Costachescu","doi":"10.1109/ESSDERC.2013.6818827","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818827","url":null,"abstract":"Advanced integrated power technologies offer DMOS transistors with substantially reduced sizes. However, a smaller device area increases the thermal impedance, lowering the maximum amount of energy the DMOS can withstand without reaching excessive temperatures and subsequent destruction. Because of this limitation, it is often not possible to fully exploit the very low area specific on-state resistances of modern integrated power technologies. The very high temperatures leading to failure are usually confined to a small region of the DMOS, while most of the active area of the device remains at a much lower temperature. By redistributing the power dissipation from the hotter to the cooler DMOS areas, the peak temperature of the transistor can be lowered without increasing the area. Thus, the device is capable of dissipating larger amounts of energy before destruction. This work presents two different approaches to improve the energy capability of DMOS transistors. Both approaches can be implemented in integrated power technologies solely by layout modifications. No changes of the fabrication process are required. Both approaches are investigated by simulations and measurements to demonstrate their effectiveness.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122564866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Full-band simulation of p-type ultra-scaled silicon nanowire transistors p型超尺度硅纳米线晶体管全带仿真
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818823
Á. Szabó, M. Luisier
{"title":"Full-band simulation of p-type ultra-scaled silicon nanowire transistors","authors":"Á. Szabó, M. Luisier","doi":"10.1109/ESSDERC.2013.6818823","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818823","url":null,"abstract":"We present in this paper a computationally efficient full-band approach to simulate the current characteristics of p-type ultra-scaled, circular, gate-all-around nanowire field-effect transistors (FETs). It is based on an extension of the semiclassical top-of-the-barrier model where tunneling is accounted for through the Wentzel-Kramers-Brillouin approximation and Poisson equation is reduced to a one-dimensional (1-D) problem. As compared to 3-D, full-band, and atomistic simulations, the computational times significantly decrease while still offering accurate device characteristics. The properties of p-type Si nanowire FETs with different crystal orientations, diameters (4-8 nm), and gate lengths (5-15 nm) are calculated as an illustration. It is found that the performance advantage of 〈110〉-oriented devices at relatively long gate lengths - thanks to a lighter transport effective mass than 〈111〉 and 〈100〉 - vanishes at short gate lengths due to an increase of the source-to-drain tunneling rate.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125247890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of IDS and mobility oscillations 8nm宽的SOI和sSOI纳米线的低温输运特性:IDS和迁移率振荡的证据
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818853
R. Coquand, S. Barraud, M. Cassé, M. Koyama, V. Maffini-Alvaro, M. Samson, L. Tosti, X. Mescot, G. Ghibaudo, S. Monfray, F. Boeuf, O. Faynot, B. D. Salvo
{"title":"Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of IDS and mobility oscillations","authors":"R. Coquand, S. Barraud, M. Cassé, M. Koyama, V. Maffini-Alvaro, M. Samson, L. Tosti, X. Mescot, G. Ghibaudo, S. Monfray, F. Boeuf, O. Faynot, B. D. Salvo","doi":"10.1109/ESSDERC.2013.6818853","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818853","url":null,"abstract":"This paper describes low-field electron transport in nanowire FETs with high-k/metal gate fabricated on 300 mm SOI and strained-SOI substrates. We studied the temperature and size dependences of gate-channel capacitance (CGc) and effective mobility (μEFF) down to 8 nm width. We show that the electron mobility is strongly reduced for sub-10 nm widths. Low-temperature measurements show a quantum oscillatory behavior of mobility revealing the electron confinement in 1D subbands structure of nanowires for temperature below 50K.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126883081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Melt depth and time variations during pulsed laser thermal annealing with one and more pulses 单脉冲和多脉冲激光热退火过程中熔体深度和时间的变化
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818857
M. Hackenberg, M. Rommel, M. Rumler, J. Lorenz, P. Pichler, K. Huet, R. Negru, G. Fisicaro, A. Magna, N. Taleb, M. Quillec
{"title":"Melt depth and time variations during pulsed laser thermal annealing with one and more pulses","authors":"M. Hackenberg, M. Rommel, M. Rumler, J. Lorenz, P. Pichler, K. Huet, R. Negru, G. Fisicaro, A. Magna, N. Taleb, M. Quillec","doi":"10.1109/ESSDERC.2013.6818857","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818857","url":null,"abstract":"In this work we present transient reflectivity measurements, maximum melt depths, and surface topographies of ion implanted silicon samples after pulsed excimer laser thermal annealing in the melting regime. The samples were annealed with different laser energies and number of pulses. We found that the melt dynamics change after the first laser pulse resulting in a shorter melt time but deeper melt depth. This can be explained by a change in reflectivity due to boron activation, surface modifications and small changes in the oxide thickness.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126913563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of T-gate stem height on parasitic gate delay time in InGaAs-HEMTs ingaas - hemt中t型栅杆高度对寄生栅延迟时间的影响
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818832
T. Yoshida, Kengo Kobayashi, T. Otsuji, T. Suemitsu
{"title":"Impact of T-gate stem height on parasitic gate delay time in InGaAs-HEMTs","authors":"T. Yoshida, Kengo Kobayashi, T. Otsuji, T. Suemitsu","doi":"10.1109/ESSDERC.2013.6818832","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818832","url":null,"abstract":"We report an impact of the stem height of T-gate electrodes on the parasitic gate delay time in InGaAs high electron mobility transistors (HEMTs). Since T-gates with higher stem height make the parasitic gate capacitance smaller, the higher stem height is expected to minimize the parasitic gate delay. However, a systematic study using the devices with different height in the stems of T-gates reveals that the parasitic gate delay decreases with the parasitic gate capacitance only at a drain voltage around the knee voltage and it becomes less sensitive to the parasitic capacitance by the T-gate when the device is operated in the deep saturation region at high drain bias voltage. This result suggests a design strategy for T-gate electrodes so that the tradeoff between the gate resistance and gate capacitance must be considered seriously in the devices for low-voltage applications, while one has more freedom to use the T-gate electrode with a large head in the devices for high-voltage applications.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115106470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A negative differential resistance effect implemented with a single MOSFET from 375 k down to 80 k 用单个MOSFET实现从375 k到80 k的负差分电阻效应
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818885
V. Vega-Gonzalez, E. Gutierrez-Dominguez, F. Guarín
{"title":"A negative differential resistance effect implemented with a single MOSFET from 375 k down to 80 k","authors":"V. Vega-Gonzalez, E. Gutierrez-Dominguez, F. Guarín","doi":"10.1109/ESSDERC.2013.6818885","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818885","url":null,"abstract":"We report the implementation of a negative resistance (NR) device with a single MOSFET. This effect is achieved by biasing a regular 28-nm n-type Metal-Oxide Field-Effect Transistor (nMOSFET) as a Bipolar Junction Transistor (BJT) with the gate left floating. The NR device has a controllable peak-to-valley current ratio (PVCR) that goes from about 1.7 up to a value of 5.5 when varying the temperature from 375 K down to 80 K. Experimental results at room temperature were compared to numerical simulations that confirm the combined action of a superficial MOS-like-driven bipolar effect with that of a volumetric bipolar action as well. This hypothesis was confirmed by the cryogenic results.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126509494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a poly silicon MEMS microphone for high signal-to-noise ratio 高信噪比的多晶硅MEMS传声器设计
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818876
A. Dehé, M. Wurzer, M. Fuldner, U. Krumbein
{"title":"Design of a poly silicon MEMS microphone for high signal-to-noise ratio","authors":"A. Dehé, M. Wurzer, M. Fuldner, U. Krumbein","doi":"10.1109/ESSDERC.2013.6818876","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818876","url":null,"abstract":"This paper reports on the state of the art silicon micromachined microphone utilizing a dual poly silicon membrane system. MEMS chips from 1.4mm down to 1.0mm side length are applied for mobile communication. Design aspects related with key performance parameters such as sensitivity, signal to noise ration and distortion are discussed. Sensitivity of - 38BV/Pa is achieved for different microphone membrane diameters. A maximum signal to noise ration of 66dB(A) for the largest system could be achieved. The perfect fit of simulation versus measurements enables deeper analysis and balancing of noise contributors. Environmental noise suppression of 5dB by acoustical high pass design is demonstrated.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124952285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Weibull analysis of the kinetics of resistive switches based on tantalum oxide thin films 基于氧化钽薄膜的电阻开关动力学的威布尔分析
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818847
Y. Nishi, S. Schmelzer, U. Böttger, R. Waser
{"title":"Weibull analysis of the kinetics of resistive switches based on tantalum oxide thin films","authors":"Y. Nishi, S. Schmelzer, U. Böttger, R. Waser","doi":"10.1109/ESSDERC.2013.6818847","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818847","url":null,"abstract":"We study the kinetics of bipolar resistive switches in tantalum oxide thin films having different thicknesses. The time to switch from the high resistance state to the low resistance state (SET) is measured repeatedly in a single cell of each sample and analyzed based on a Weibull distribution. In the thin film device the Weibull parameter fJ> 1 is observed in the short time region, followed by a distribution with ß <; 1 in the long time region. This indicates that a progressing phenomenon induces the SET action in the short time region, while it is saturated in the long time region, where the SET is triggered by a sporadic event. In the thick film sample a distribution with ß<; 1 is dominant almost in the whole time range. Further analysis revealed that the heat generated before the switch-on can be responsible for the SET in the fJ> 1 mode.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126329636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Design and array implementation a cantilever-based non-volatile memory utilizing vibrational reset 利用振动复位的基于悬臂的非易失性存储器的设计和阵列实现
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818874
A. Do, K. G. Jayaraman, Pushpapraj Singh, C. Li, K. Yeo, T. T. Kim
{"title":"Design and array implementation a cantilever-based non-volatile memory utilizing vibrational reset","authors":"A. Do, K. G. Jayaraman, Pushpapraj Singh, C. Li, K. Yeo, T. T. Kim","doi":"10.1109/ESSDERC.2013.6818874","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818874","url":null,"abstract":"This paper proposes a cantilever-based memory structure for storing binary data at extreme operating temperature (up to 300°C) in rugged electronics. The memory bit (0/1) is formed by opening/closing of an electrostatic switch. Permanent retention is obtained by adhesive force between two smooth surfaces in contact, eliminating leakage observed in all types of storage-layer-based NVMs. The Reset utilizes a train of short pulses to break the adhesion between the electrodes. This allows the Nano-electromechanical switch (NEMS) memory to be implemented using a simple bi-layer design and easily integrated with CMOS platforms. We propose an array structure where each memory cell consists of a NEMS memory device and one NMOS transistor for full random-access operation.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"30 Suppl 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130799637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On-wafer graphene diodes for high-frequency applications 用于高频应用的片上石墨烯二极管
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818883
M. Dragoman, A. Dinescu, D. Dragoman
{"title":"On-wafer graphene diodes for high-frequency applications","authors":"M. Dragoman, A. Dinescu, D. Dragoman","doi":"10.1109/ESSDERC.2013.6818883","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818883","url":null,"abstract":"This manuscript presents the theory, the fabrication and the initial measurements of geometric diodes made on a graphene monolayer. The fabrication process is done on-wafer, in deep contrast with the majority of graphene devices, which are fabricated on small graphene flakes. The first estimations show that the cut-off frequency of this device is 6.5 THz.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132942062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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