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2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)最新文献

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A Pipelined Speed Enhancement Technique for CDAC-Threshold Configuring SAR ADC 基于cdac阈值配置SAR ADC的流水线速度增强技术
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585708
Mustafa Kilic, Y. Leblebici
{"title":"A Pipelined Speed Enhancement Technique for CDAC-Threshold Configuring SAR ADC","authors":"Mustafa Kilic, Y. Leblebici","doi":"10.1109/NEWCAS.2018.8585708","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585708","url":null,"abstract":"In this paper, a novel SAR ADC architecture enabling very high speed operation is presented. Based on a hybrid capacitive DAC-threshold configuring scheme, the proposed architecture performs conversions in two-stages, similarly to pipelined ADCs. An additional set of threshold configuring comparators is inserted for pipeline configuration. While the MSBs are computed during the first stage via the capacitive DAC and the first set of comparators, the LSBs of the previous sample are extracted by the second set of comparators via threshold configuration. This leads to an increased throughput and the overall sampling speed is boosted. Unlike to conventional pipelined topologies, this architecture does not require residue amplification. An 8-bit SAR ADC with asynchronous logic and alternate comparators has been implemented in a 28 nm FDSOI technology with this architecture. The ADC achieves a sampling rate of 1.8GS/s while consuming 5.77mW.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114488898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 17-bit 104-dB-DR High-Precision Low-Power CMOS Fluorescence Biosensor With Extended Counting ADC and Noise Cancellation 一种17位104 db - dr高精度低功耗CMOS荧光生物传感器，具有扩展计数ADC和降噪功能
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585682
M. N. Khiarak, K. Sasagawa, T. Tokuda, J. Ohta, S. Martel, Y. Koninck, B. Gosselin
{"title":"A 17-bit 104-dB-DR High-Precision Low-Power CMOS Fluorescence Biosensor With Extended Counting ADC and Noise Cancellation","authors":"M. N. Khiarak, K. Sasagawa, T. Tokuda, J. Ohta, S. Martel, Y. Koninck, B. Gosselin","doi":"10.1109/NEWCAS.2018.8585682","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585682","url":null,"abstract":"This paper presents a high-dynamic range CMOS biosensor fusing a photosensing module with a high-precision extended counting analog-to-digital converter (ADC) with noise cancellation to detect florescence neural signal fluctuations of very low incident power. The 7 MSBs are resolved by a first order continuous-time resettable $Sigma triangle mathrm {A}mathrm {D}mathrm {C}$, whereas the residue voltage is quantized by a 10-bit single slope ADC for enabling wide dynamic range and high precision fluorescence sensing. Low-frequency imperfections are canceled out by an embedded noise cancellation scheme which is subtracting the noise and the offset using switches and capacitors. The quantizer is shared between the $Sigma triangle $ and the single slope ADC to decrease the chip size and to improve energy-efficiency. The proposed optoelectronic biosensor is implemented in a $0.18-mu mathrm {m}$ CMOS technology, consuming $93 mu mathrm {W}$ from a 3.3-V supply voltage while achieving a DR of 104dB, and a minimum detectable current of $400-fA_{rms}$, for a conversion time of $506.5mu s.$","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124078057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors 使用加法器压缩器的低功耗HEVC 8点二维离散余弦变换硬件
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585470
Luis F. Sequeira, Gustavo Madeira Santana, Guilherme Paim, L. G. Rocha, B. Abreu, E. Costa, S. Bampi
{"title":"Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors","authors":"Luis F. Sequeira, Gustavo Madeira Santana, Guilherme Paim, L. G. Rocha, B. Abreu, E. Costa, S. Bampi","doi":"10.1109/NEWCAS.2018.8585470","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585470","url":null,"abstract":"This paper presents a low-power hardware architecture for the HEVC Discrete Cosine Transform stage implemented using power-efficient adder compressors. The proposed hardware architecture manages to save hardware resources through an optimized organization and improves energy efficiency. The hardware design was described in Verilog HDL (Hardware Description Language) and synthesized for ASIC technology using the Cadence Genus Synthesis tool. The synthesis results were generated with a realistic ASIC-based methodology and demonstrates that the developed architecture saves up to 14.76% of power dissipation, and 13.99% in circuit area when implemented with efficient adder compressors and compared to conventional adders.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124968643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low-Cost 3D-Printed PLA-COC Micro Hydrodynamic Focused Device 低成本3d打印PLA-COC微流体动力聚焦装置
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585663
R. López, V. Nerguizian, I. Stiharu
{"title":"Low-Cost 3D-Printed PLA-COC Micro Hydrodynamic Focused Device","authors":"R. López, V. Nerguizian, I. Stiharu","doi":"10.1109/NEWCAS.2018.8585663","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585663","url":null,"abstract":"3D-printing has recently attracted the interest of researchers in microfluidics. This technology has proved its potential as a way of fabricating microchannels offering an automated, low-cost, and straight-forward approach compared with the laborious soft-lithography method. 3D-printing enables rapid prototyping. Microfluidic devices can be produced using Fused Deposition Modeling (FDM), with channels width in the order of hundreds of micrometers. These devices can be used for testing new topologies, geometries, and concepts, before investing in others costlier methods. The study of the flow inside microfluidic devices requires optical access to microchannels. Unfortunately, even transparent materials such as Poly Lactic Acid (PLA) produce translucent 3D prints, that are not optically transparent, because of the layering process in 3D-printing. In this work, we propose a way of creating an optical window by using an open channel approach delimited by Cyclic Olefin Copolymer (COC). This approach enabled us to monitor liquid flow inside the device using biocompatible materials.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128319552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power-Silicon Efficient All-Digital △Σ TDC with Differential Gated Delay Line Time Integrator 功率硅高效全数字△Σ带差分门控延迟线时间积分器的TDC
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585621
Parth Parekh, F. Yuan
{"title":"Power-Silicon Efficient All-Digital △Σ TDC with Differential Gated Delay Line Time Integrator","authors":"Parth Parekh, F. Yuan","doi":"10.1109/NEWCAS.2018.8585621","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585621","url":null,"abstract":"This paper presents an all-digital 1st-order 1-bit $Delta Sigma $ time-to-digital converter (TDC). A single-step integration method is proposed to perform differential time integration using a bi-directional gated delay line (BDGDL) to reduce integration time. An in-depth investigation into the impact of process uncertainty on the TDC is provided. The TDC is designed in an IBM 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM4 device models. The simulation results of the TDC with a 244 kHz sinusoidal input of amplitude 333 ps over frequency range from flicker noise corner frequency to 3rd-order harmonic frequency demonstrate that the TDC provides SNDR of 39.8 dB and time resolution of 4.2 ps while consuming 396.6 μW. The figure-of-merit (FOM) of the TDC is 3.6 pJ/step, better that of reported TDCs alike. The effect of process uncertainty on the TDC can be minimized by tuning the delay blocks of the TDC.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129589944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Methodology for the Design of Capacitive Feedback LNAs based on the gm/ID Characteristic 基于gm/ID特性的电容反馈lna设计方法
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585612
Jing Liu, E. Lauga-Larroze, Serge Subias, J. Fournier, S. Bourdel, C. Galup-Montoro, F. Hameau
{"title":"A Methodology for the Design of Capacitive Feedback LNAs based on the gm/ID Characteristic","authors":"Jing Liu, E. Lauga-Larroze, Serge Subias, J. Fournier, S. Bourdel, C. Galup-Montoro, F. Hameau","doi":"10.1109/NEWCAS.2018.8585612","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585612","url":null,"abstract":"This paper presents a $g_{n}sqrt {}I_{D}$ based design methodology for a capacitive feedback LNA topology. The proposed method gives the optimal value of $g_{n}sqrt {}I_{D}$ to achieve the required performances (Gain and Noise Figure) while ensuring the minimum consumption. Moreover, it makes possible the sizing of all the components of the structure with a degree of freedom for the inductance value needed for the input power matching. This methodology is illustrated through the design of a $2. 4mathrm {G}mathrm {H}mathrm {z}$ LNA in the $28mathrm {n}mathrm {m}$ FDSOI technology from ST-Microelectronics.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125420088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Enhancement of sensitivity of detecting growth hormones through nano integration of lab on chips 芯片上实验室纳米集成技术提高生长激素检测灵敏度
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585724
J. Ozhikandathil, S. Badilescu, M. Packirisamy
{"title":"Enhancement of sensitivity of detecting growth hormones through nano integration of lab on chips","authors":"J. Ozhikandathil, S. Badilescu, M. Packirisamy","doi":"10.1109/NEWCAS.2018.8585724","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585724","url":null,"abstract":"The bovine growth hormone is a common growth promoter used in dairy farming to enhance the milk production. Its use is forbidden in Canada, the European Union and many other countries because the hormone could be harmful to the health of animals and humans. For this reason, it is important to develop fast and low-cost methods of detection of the bovine growth hormone at very low concentrations. Conventional methods as well as the recent developments of lab-on-a-chip technologies are reviewed with an emphasis of the work in our laboratory.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123388615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
HPQ: A High Capacity Hybrid Priority Queue Architecture for High-Speed Network Switches 高速网络交换机的高容量混合优先队列结构
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585434
Imad Benacer, F. Boyer, Y. Savaria
{"title":"HPQ: A High Capacity Hybrid Priority Queue Architecture for High-Speed Network Switches","authors":"Imad Benacer, F. Boyer, Y. Savaria","doi":"10.1109/NEWCAS.2018.8585434","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585434","url":null,"abstract":"This paper presents a fast hybrid priority queue architecture usable in todays high-speed networking devices. This architecture can be used for scheduling and prioritizing packets in the network data plane. Due to increasing traffic, a high capacity priority queue, with constant latency and guaranteed performance is highly needed. In this work, an important goal is to reduce latency to best support the upcoming 5G wireless standards. The proposed hybrid priority queue architecture enables pipelined en/dequeue operations with O(1) time complexity. The proposed architecture is implemented in ${C}+ quad +$ and is synthesized with the Vivado High-Level Synthesis tool. The reported results show the feasibility of the proposed solutions and are compared across a range of priority queue depths and performance metrics with existing approaches. An implementation of the proposed architecture on a ZC706 FPGA board works at 60 MHz and supports links operating at 10 Gb/s, with a total capacity of ${frac {1}{2}}$ million packet tags spread over 512 independent queues.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116077951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Model-Based Approach for the Design of Ultra-Low Power Wireless Sensor Nodes 基于模型的超低功耗无线传感器节点设计方法
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585492
Oussama Brini, D. Deslandes, F. Nabki
{"title":"A Model-Based Approach for the Design of Ultra-Low Power Wireless Sensor Nodes","authors":"Oussama Brini, D. Deslandes, F. Nabki","doi":"10.1109/NEWCAS.2018.8585492","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585492","url":null,"abstract":"This paper presents a model-based approach for the design of ultra-low power wireless sensor nodes along with a high-level of abstraction modeling framework based on Simulink/StateFlow. This leads to a fast and effective method of designing low-power wireless sensing systems by serving as a guideline for choosing the right commercial off-the-shelf (COTS) components and node configuration. Through simulations, the impact of using different configurations on energy and power consumption metrics is determined, and the models capture the energy consumption contributions of each of the studied components.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122774725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Feasible Assignment of Micro-Bumps in 3D ICs 三维集成电路中微凸点的可行分配
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585566
Jin-Tai Yan, Chia-Heng Yen
{"title":"Feasible Assignment of Micro-Bumps in 3D ICs","authors":"Jin-Tai Yan, Chia-Heng Yen","doi":"10.1109/NEWCAS.2018.8585566","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585566","url":null,"abstract":"For the signal connections between two adjacent dies in 3D ICs, the redistributed layers (RDLs) routing from IO pads to micro-bumps plays an important role. In this paper, given a set of nets on the upper and lower RDLs between two adjacent dies, based on the separation of one 2-pin net on the upper and lower RDLs using one micro-bump, an efficient two-phase algorithm can be proposed to assign feasible micro-bumps onto the nets to minimize the overlapping degree and the X-type intersections on the routing regions for single-layer RDL routing. Compared with Kuan’s algorithm and Yan’s algorithm in the micro-bump assignment for single-layer RDL routing, the experimental results show that our proposed algorithm can use less CPU time to assign feasible micro-bumps onto the given nets and obtain 100% routability with shorter wirelength in 5 tested examples.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127776144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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