A Pipelined Speed Enhancement Technique for CDAC-Threshold Configuring SAR ADC

Abstract

In this paper, a novel SAR ADC architecture enabling very high speed operation is presented. Based on a hybrid capacitive DAC-threshold configuring scheme, the proposed architecture performs conversions in two-stages, similarly to pipelined ADCs. An additional set of threshold configuring comparators is inserted for pipeline configuration. While the MSBs are computed during the first stage via the capacitive DAC and the first set of comparators, the LSBs of the previous sample are extracted by the second set of comparators via threshold configuration. This leads to an increased throughput and the overall sampling speed is boosted. Unlike to conventional pipelined topologies, this architecture does not require residue amplification. An 8-bit SAR ADC with asynchronous logic and alternate comparators has been implemented in a 28 nm FDSOI technology with this architecture. The ADC achieves a sampling rate of 1.8GS/s while consuming 5.77mW.