2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)最新文献_第3页

Identifying and Exploiting Ineffectual Computations to Enable Hardware Acceleration of Deep Learning 识别和利用无效计算实现深度学习的硬件加速

2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585656

Andreas Moshovos, Jorge Albericio, Patrick Judd, A. Delmas, Sayeh Sharify, M. Mahmoud, Tayler H. Hetherington, M. Nikolic, Dylan Malone Stuart, Kevin Siu, Zissis Poulos, Tor M. Aamodt, Natalie D. Enright Jerger

{"title":"Identifying and Exploiting Ineffectual Computations to Enable Hardware Acceleration of Deep Learning","authors":"Andreas Moshovos, Jorge Albericio, Patrick Judd, A. Delmas, Sayeh Sharify, M. Mahmoud, Tayler H. Hetherington, M. Nikolic, Dylan Malone Stuart, Kevin Siu, Zissis Poulos, Tor M. Aamodt, Natalie D. Enright Jerger","doi":"10.1109/NEWCAS.2018.8585656","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585656","url":null,"abstract":"This article summarizes somde of our work on hardware accelerators for inference with Deep Learning Neural Networks (DNNs). Early success in hardware acceleration for DNNs exploited the computation structure and the significant reuse in their access stream. Our approach to further boost benefits has been to first identify properties in the value stream of DNNs which we can exploit at the hardware level to improve execution time, reduce off- and on-chip communication and storage, resulting in higher energy efficiency and execution time reduction. We have been focusing on properties that are difficult or impossible to discern in advance. These properties include values that are zero or near zero and that prove ineffectual, values that have reduced precision needs, or even the bit-level content of values that lead to ineffectual computations. The presented designs cover a spectrum of choices in terms of area cost, energy efficiency, and relative execution time performance and target a variety of hardware devices from embedded systems to server class machines. A key characteristic of these designs is that they reward but do not requires advances in model design that increase the aforementioned properties (such as reduced precision or sparsity) and thus provide a safe path to innovation.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134456200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Wide Input Range Single Feed RF Energy Harvester 宽输入范围单馈射频能量采集器

2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585489

S. Nagaveni, Bibhudatta Sahoo, A. Dutta

引用次数: 0

Virtual prototyping of biosensors involving reaction- diffusion phenomena 涉及反应扩散现象的生物传感器虚拟样机

2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585653

M. Madec, Alexi Bonament, Elise Rosati, L. Hébrard, C. Lallement

引用次数: 2

THz Ballistic Deflection Transistor Travelling Wave Amplifier Design with THz Ring Hybrid Coupler 太赫兹弹道偏转晶体管行波放大器与太赫兹环混合耦合器的设计

2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585496

Huan Wang, J. Millithaler, M. Margala, R. Knepper

引用次数: 0

A 0.35V 12.9pW 8.3ppm°C 0.012%/V Feedbackcontrolled Voltage Reference in 65 nm CMOS 一个0.35V 12.9pW 8.3ppm°C 0.012%/V 65nm CMOS反馈控制电压基准

2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585688

A. Azam, Zhidong Bai, D. Korth, J. Walling

引用次数: 1

Utilizing Dynamic Partial Reconfiguration to Reduce the Cost of FPGA Debugging 利用动态部分重构降低FPGA调试成本

2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585494

Islam Ahmed, Ahmed Kamaleldin, H. Mostafa, A. Mohieldin

{"title":"Utilizing Dynamic Partial Reconfiguration to Reduce the Cost of FPGA Debugging","authors":"Islam Ahmed, Ahmed Kamaleldin, H. Mostafa, A. Mohieldin","doi":"10.1109/NEWCAS.2018.8585494","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585494","url":null,"abstract":"Debugging of Field-Programmable Gate Arrays (FPGAs) is a difficult task due to the limited access to the internal signals of the design. Embedded logic analyzers enhance the signal observability for FPGAs. These analyzers are implemented on the FPGA resources and they use the embedded memory blocks as trace buffers, so a limited number of signals can be observed using these analyzers due to resources constraints. Changing the traced set of signals requires re-synthesis, placement and routing of the whole design. In this paper, we propose a new methodology for FPGA debugging to change dynamically the set of signals to be observed at runtime, and consequently minimize the time required for debugging. The proposed methodology utilizes the Dynamic Partial Reconfiguration (DPR) technique to dynamically switch between different sets of signals. DPR creates a reconfigurable module (RM) to route each set of signals to an embedded logic analyzer. We demonstrate the proposed approach using Xilinx FPGA tools, finding that changing the set of signals to be observed requires only few milli-seconds to re-program the reconfigurable region (RR). The area overhead of the proposed methodology is lower than other traditional methods of using multiplexers as the DPR allows the routing module to only use buffers to connect a set of signals to the embedded logic analyzer.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124518988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A 500 pW 16 KHz Injection Locked Oscillator for Ultra-Low Power Time-Domain ADC Application 用于超低功耗时域ADC应用的500pw 16khz注入锁定振荡器

2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585520

N. Goux, E. Dina, F. Badets

引用次数: 1

A Wide-Load-Range Mixed-Mode LDO Regulator with Single-Transistor-Assisted Buffer 带单晶体管辅助缓冲器的宽负载范围混合模式LDO稳压器

2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585690

Ning Zhang, Chenchang Zhan, Han Li, Linjun He

{"title":"A Wide-Load-Range Mixed-Mode LDO Regulator with Single-Transistor-Assisted Buffer","authors":"Ning Zhang, Chenchang Zhan, Han Li, Linjun He","doi":"10.1109/NEWCAS.2018.8585690","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585690","url":null,"abstract":"A wide-load-range low-dropout (LDO) regulator with single-transistor-assisted buffer and analog-digital mixed-mode control is presented in this paper. The single-transistor-assisted PMOS-input unity-gain-buffer can extend the gate voltage range of the analog power transistor and guarantee that the proposed LDO regulator can work well even at very light load current. To extend the loading capability for large load current, a mixed-mode control is used to detect heavy load and turn on or off the digital power transistor which provides large current to the load with better area efficiency. With the digital assistance, the proposed LDO regulator has better load regulation and loading capability at heavy load as well. A proof-of-concept design of the proposed LDO regulator has been implemented and fabricated in a standard $0.18-mu mathrm {m}$ CMOS process. It occupies an active area of only $0.01 mathrm {m}mathrm {m}^{2}$. With the load current step from 0 mA to 150 mA, the proposed LDO regulator with digital assistance achieves a droop voltage reduction of more than 50% compared to the design without the digital assistance. A load regulation of 0.21 mV/mA is achieved by the proposed design with the help of the digital assistance and single-transistor-assisted buffer.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"1093 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116042173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of CMOS LNA with the Inversion Coefficient 带反转系数的CMOS LNA设计

2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585633

G. Guitton, T. Taris, Marcelo de Souza, A. Mariano

引用次数: 4

Microfluidic H-filter Cell Modeling for Robust Purification of Gold Nanoparticles 金纳米颗粒鲁棒提纯的微流控h -过滤器模型

2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585579

Shimwe Dominique Niyonambaza, Élodie Boisselier, M. Boukadoum, A. Miled

引用次数: 1