Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors

Abstract

This paper presents a low-power hardware architecture for the HEVC Discrete Cosine Transform stage implemented using power-efficient adder compressors. The proposed hardware architecture manages to save hardware resources through an optimized organization and improves energy efficiency. The hardware design was described in Verilog HDL (Hardware Description Language) and synthesized for ASIC technology using the Cadence Genus Synthesis tool. The synthesis results were generated with a realistic ASIC-based methodology and demonstrates that the developed architecture saves up to 14.76% of power dissipation, and 13.99% in circuit area when implemented with efficient adder compressors and compared to conventional adders.