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Linear finite state machine for lD ILAs ldas的线性有限状态机
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292293
M. Gala, P. Utama, D. Ross, K. Watson
{"title":"Linear finite state machine for lD ILAs","authors":"M. Gala, P. Utama, D. Ross, K. Watson","doi":"10.1109/VTEST.1994.292293","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292293","url":null,"abstract":"Linear Finite State Machine for One Dimensional (1D) Iterative Logic Arrays (ILAs) is described. The technique for modifying the Linear Feedback Shift Register (LFSR) based test generator called Linear Finite State Machine (LFSM) for deterministic test pattern generation is discussed and extended for generating the test vectors for 1D unilateral ILAs. One Repetition Length (ORL) of C-testable ILAs and unique characteristics of the C-testable test patterns are used for the compact design of the LFSM based at-speed Built-in Self Test (BIST). Such LFSM based BIST occupies small silicon area, simplifies the design of the controller and does at-speed testing of the ILAs. This results in reduced time and cost of testing. In addition, the exact probability distribution equations are developed for additional bits needed to map a Finite State Machine (FSM) into an LFSM. The distribution clearly shows that the expected number of additional bits is very small, often zero. The probability distribution equations are equally valid for any LFSR based test generator for other circuits.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121103480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Impact of behavioral modifications for testability 行为修改对可测试性的影响
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292278
T. Thomas, P. Vishakantaiah, J. Abraham
{"title":"Impact of behavioral modifications for testability","authors":"T. Thomas, P. Vishakantaiah, J. Abraham","doi":"10.1109/VTEST.1994.292278","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292278","url":null,"abstract":"Behavioral specification of a VLSI design can be used to suggest behavioral modifications that improve testability of the design. Past work has been targeted at identifying the techniques that will enable such modifications. However, the impact of such behavioral modifications on the testability of a design has not been analyzed with regards to fault coverage and area overhead which is the focus of this paper. Results obtained show that the area overhead is low and the fault coverage is higher when the behavior is modified for testability. These results are compared with the results obtained when partial scan is used to improve the testability of a design.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115533207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
On compacting test sets by addition and removal of test vectors 用测试向量的加减法压缩测试集
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292312
S. Kajihara, I. Pomeranz, K. Kinoshita, S. Reddy
{"title":"On compacting test sets by addition and removal of test vectors","authors":"S. Kajihara, I. Pomeranz, K. Kinoshita, S. Reddy","doi":"10.1109/VTEST.1994.292312","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292312","url":null,"abstract":"This paper presents a method of test compaction for stuck-at faults in combinational circuits, that complements previously proposed methods and allows further reduction in test set size in a cost-effective way. A given test set is compacted by generating additional test vectors. Each test vector added allows the removal of two or more test vectors from the existing test set, thus reducing its size. Experimental results for benchmark circuits demonstrate the effectiveness of the method.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115571765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Synthesizing designs with low-cardinality minimum feedback vertex set for partial scan application 面向部分扫描应用的低基数最小反馈顶点集综合设计
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292342
S. Dey, M. Potkonjak, R. Roy
{"title":"Synthesizing designs with low-cardinality minimum feedback vertex set for partial scan application","authors":"S. Dey, M. Potkonjak, R. Roy","doi":"10.1109/VTEST.1994.292342","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292342","url":null,"abstract":"An efficient partial scan approach for cost-effective sequential ATPG is to select flip-flops (FFs) in the minimum feedback vertex set (MFVS) of the FF dependency graph, so that loops are broken. Through a comprehensive analysis of the sources of loops in the data path, this paper proposes a new high-level synthesis methodology to synthesize data paths which have low-cardinality MFVS, thereby reducing the cost of partial scan significantly. A test efficiency of 100% could be achieved for all designs synthesized by the proposed approach, requiring a significantly less number of FFs to be scanned compared to the original implementations.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129268790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Fault detection and fault localization using I/sub DDQ/-testing in parallel testable FAST-SRAMs 基于I/sub DDQ/-测试的并行可测试fast - sram故障检测与故障定位
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292285
C. Elm, D. Tavangarian
{"title":"Fault detection and fault localization using I/sub DDQ/-testing in parallel testable FAST-SRAMs","authors":"C. Elm, D. Tavangarian","doi":"10.1109/VTEST.1994.292285","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292285","url":null,"abstract":"This paper contributes to the area of I/sub DDQ/-testing of SRAMs by extending fault detection to transition coupling and neighborhood pattern sensitive faults. Furthermore I/sub DDQ/-testing is expanded to fault localization. To accelerate existing test procedures of RAMs, associative search based test algorithms are modified with I/sub DDQ/-testability for use in so called FAST-RAMs, which are designed to be tested in parallel. This method reduces the complexity of existing test algorithms by one or two orders. The chip area to implement FAST-testability runs up to a few per cent or per mille depending on the RAM architecture. Circuit details are discussed and compared with existing SRAM testing.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124484297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
FACTS: fault coverage estimation by test vector sampling 事实:故障覆盖估计通过测试向量采样
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292302
Keerthi Heragu, V. Agrawal, M. Bushnell
{"title":"FACTS: fault coverage estimation by test vector sampling","authors":"Keerthi Heragu, V. Agrawal, M. Bushnell","doi":"10.1109/VTEST.1994.292302","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292302","url":null,"abstract":"We propose a new statistical technique for estimating fault coverage in combinational circuits. Our method requires fault-free simulation of a random sample of vectors from the test vector set. Fault coverage is computed from controlabilities and observabilities both defined as probabilities and the method is applicable to any fault model like stuck-at-faults or delay faults. Experimental results are presented for path and transition delay faults.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127593597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Design for testability of on-line multipliers 在线乘法器的可测试性设计
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292281
H. Bederr, M. Nicolaidis, A. Guyot
{"title":"Design for testability of on-line multipliers","authors":"H. Bederr, M. Nicolaidis, A. Guyot","doi":"10.1109/VTEST.1994.292281","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292281","url":null,"abstract":"This paper deals with the test of an integrated on-line multiplier suitable for very large numbers. Due to the serial structure of the circuit, the controllability and observability of the different elements are very low. In particular, an embedded sequential array cannot be accessed directly and has no primary outputs. Therefore, we propose here two DFT alternatives. The first one determines the most significant nodes to be considered in order to avoid error masking. The second approach increases the parallelism of the circuit and presents, thus, the advantage of a large reduction in the test duration. Both options have a low area overhead and a reduced number of extra pins.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114319883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ICAT: incremental combinational ATPG ICAT:增量组合ATPG
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292326
B. So, C. Kime
{"title":"ICAT: incremental combinational ATPG","authors":"B. So, C. Kime","doi":"10.1109/VTEST.1994.292326","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292326","url":null,"abstract":"An incremental ATPG system for combinational circuits, ICAT, is presented. ICAT uses the hypothesis that, if a circuit modification is small, the old tests for the circuit before modification can provide crucial information to speed up generation of new tests for the modified circuit. Four incremental techniques in ICAT maximally utilize information from the old tests with minimal storage requirements. The four incremental techniques are augmented with a fast, effective deterministic test generation algorithm in ICAT. The experimental results from the evaluation of three different classes of modifications to ISCAS circuits show the incremental technique to be efficient and effective.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114918005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An industrial experience in the built-in self test of embedded RAMs 具有嵌入式ram内置自检的行业经验
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292296
P. Camurati, P. Prinetto, M. Reorda, S. Barbagallo, A. Burri, D. Medina
{"title":"An industrial experience in the built-in self test of embedded RAMs","authors":"P. Camurati, P. Prinetto, M. Reorda, S. Barbagallo, A. Burri, D. Medina","doi":"10.1109/VTEST.1994.292296","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292296","url":null,"abstract":"High-quality embedded memory testing is increasingly important and a BIST scheme seems advantageous. Industrial experience at Italtel, a telecom company, confirms it. The scheme implements in hardware the test pattern generation algorithm proposed by R. Nair, S.M. Thatte, and J.A. Abraham /spl lsqb/1978/spl rsqb/, extending it to word-based memories. Several goodness criteria are satisfied, as the experimental results confirm.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125053472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
On-line delay testing of digital circuits 数字电路的在线延迟测试
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292318
P. Franco, E. McCluskey
{"title":"On-line delay testing of digital circuits","authors":"P. Franco, E. McCluskey","doi":"10.1109/VTEST.1994.292318","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292318","url":null,"abstract":"A new technique for on-line checking of digital systems is proposed. It is shown that, under certain timing restrictions, an off-line delay-fault testing method called Stability Checking can be used for on-line checking. Efficient CMOS on-line Stability Checker designs are presented, and an algorithm for meeting timing restrictions is described. Benchmark results are shown. On-line Stability Checkers detect errors caused by most common reliability failures and transients, and are shown to perform almost as well as duplication at a fraction of the hardware cost. Since outputs are checked independently, good diagnosability is possible.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132100755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 75
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