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Proceedings of IEEE VLSI Test Symposium最新文献

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A new strategy for testing analog filters 一种新的模拟滤波器测试策略
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292337
D. Vázquez, A. Rueda, J. Huertas
{"title":"A new strategy for testing analog filters","authors":"D. Vázquez, A. Rueda, J. Huertas","doi":"10.1109/VTEST.1994.292337","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292337","url":null,"abstract":"A new strategy for testing analog filters is presented, based on the reevaluation of the transfer function followed by simple processing of the output signals. Taking advantage of the structural properties of some universal biquads, this new strategy consists in provoking pole-zero cancellation during the test mode, without eliminating information about parameters which determine the normal circuit operation. Although area overhead could seem high, it can be very small in many applications.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130275337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
A design-for-test technique for switched-capacitor filters 开关电容滤波器的测试设计技术
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292336
M. Soma, V. Kolarik
{"title":"A design-for-test technique for switched-capacitor filters","authors":"M. Soma, V. Kolarik","doi":"10.1109/VTEST.1994.292336","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292336","url":null,"abstract":"The paper describes a design-for-test technique for switched-capacitor (SC) filters to improve controllability and observability of internal nodes. Timing strategies employing existing clock phases in SC circuits are used to sensitize signal propagating paths, thus enhancing the circuit testability. The overhead in terms of extra control logic is small (several simple gates). Since there are no extraneous devices inserted in the analog signal path, there is no performance penalty in the normal operation of the filters.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121308555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
Analyzing the design-for-test techniques in a multiple substrate MCM 多基板MCM的测试设计技术分析
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292288
J. Jorgenson, R. Wagner
{"title":"Analyzing the design-for-test techniques in a multiple substrate MCM","authors":"J. Jorgenson, R. Wagner","doi":"10.1109/VTEST.1994.292288","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292288","url":null,"abstract":"This paper discusses the results of several design-for-testability techniques implemented in a multichip module (MCM). MCM test issues discussed include boundary scan, Built-In-Self-Test (BIST), concurrent test sequencing, and module level test. Analyzing the results of the DFT attributes is necessary to determine effectiveness of the overall test strategy, improve upon various techniques, and learn lessons that may be carried into subsequent generations of MCM design. A discussion of the analysis and the lessons learned is presented, as well as a brief discussion on future planned implementations.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121345802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Delay-fault testability preservation of the concurrent decomposition and factorization transformations 并发分解和分解变换的延迟故障可测性保持
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292340
A. El-Maleh, J. Rajski
{"title":"Delay-fault testability preservation of the concurrent decomposition and factorization transformations","authors":"A. El-Maleh, J. Rajski","doi":"10.1109/VTEST.1994.292340","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292340","url":null,"abstract":"Recently, a new, very efficient method of multilevel logic synthesis based on factorization and decomposition of Boolean expressions has been introduced. It has been shown that the transformations used by this method preserve the single stuck-at testability of two-level circuits. This paper shows that single-cube extraction, double-cube extraction, and dual-extraction of double-cubes/spl isin/D/sub 1,1,2/ and D/sub 2,2,2/ preserve testability with respect to a general robust path-delay-fault (RPDF) test set. However, the authors show that while dual-extraction of double-cubes/spl isin/D/sub 2,2,3/ preserves RPDF testability of paths through the extracted divisors with respect to a single-input-changing test set, it does not guarantee RPDF testability preservation of unmodified paths. Furthermore, the authors provide sufficient conditions for algebraic resubstitution with complement to preserve RPDF testability that cover a larger class of complementary expressions than was known previously. The testability preservation of these transformations is demonstrated on a set of RPDF testable Berkeley PLAs.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121545176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Boundary-scan: beyond production test 边界扫描:超出生产测试
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292280
R.M. Sedmark
{"title":"Boundary-scan: beyond production test","authors":"R.M. Sedmark","doi":"10.1109/VTEST.1994.292280","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292280","url":null,"abstract":"The use of boundary-scan, as specified in IEEE 1149.1-1990, has always been considered a source of major benefits for the production test process. However, there are many existing and potential applications of boundary-scan during other life cycle phases of a product/spl minus/the design phase and field operation and support phase. This paper focuses on these additional phases of boundary-scan application.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134345356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Realization of fully path-delay-fault testable non-scan sequential circuits 全路径延迟故障可测非扫描顺序电路的实现
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292300
W. Ke, P. R. Menon
{"title":"Realization of fully path-delay-fault testable non-scan sequential circuits","authors":"W. Ke, P. R. Menon","doi":"10.1109/VTEST.1994.292300","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292300","url":null,"abstract":"We present a new approach to synthesizing fully path-delay-fault testable non-scan sequential circuits. Two methods are proposed. Given the state transition graph of a finite state machine, one of our methods generates a fully robustly testable circuit while the other method, which may lead to more area-efficient circuits, guarantees robust or validatable non-robust tests for all paths.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133474771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Efficient UBIST for RAMs 公羊的高效UBIST
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292319
M. Nicolaidis
{"title":"Efficient UBIST for RAMs","authors":"M. Nicolaidis","doi":"10.1109/VTEST.1994.292319","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292319","url":null,"abstract":"First presents a self-checking implementation for RAMs. Then, the unified BIST technique is applied to this scheme. It merges self-checking and BIST techniques and allows a high fault coverage for all tests needed for integrated circuits, e.g. off-line test (manufacturing and maintenance test) and periodic as well as concurrent on-line testing. In order to preserve the RAM contents for periodic on-line testing the authors employ a transparent BIST implementation.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122966188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Incorporating IDDQ testing in BIST: improved coverage through test diversity 在BIST中结合IDDQ测试:通过测试多样性提高覆盖率
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292286
A. Singh, J. P. Hurst
{"title":"Incorporating IDDQ testing in BIST: improved coverage through test diversity","authors":"A. Singh, J. P. Hurst","doi":"10.1109/VTEST.1994.292286","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292286","url":null,"abstract":"A scheme for improving test coverage of traditional built-in self-test (BIST) methods through test diversity by combining IDDQ testing with BIST is described in this paper. To support the test diversity approach, the authors present a new differential architecture for built-in current sensing (BICS) which mitigates some of the performance limitations of previous designs and allows at-speed testing for practically-sized circuit partitions. A test circuit incorporating the IDDQ testing elements of the new BIST architecture has been fabricated through MOSIS, using 2.0-micron n-well technology. Results of tests performed on the actual circuit show that it accurately detects all of the test faults implanted in the circuit at speeds of up to 31.25 MHz. The test design establishes the feasibility of incorporating IDDQ testing in a realistic at-speed BIST environment.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131900266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Analysis of I/sub DDQ/ detectable bridges in combinational CMOS circuits 组合CMOS电路中I/sub DDQ/可检测桥的分析
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292287
E. Isern, J. Figueras
{"title":"Analysis of I/sub DDQ/ detectable bridges in combinational CMOS circuits","authors":"E. Isern, J. Figueras","doi":"10.1109/VTEST.1994.292287","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292287","url":null,"abstract":"Functionally equivalent nodes may cause some bridging faults to become undetectable by I/sub DDQ/ testing. An efficient method for the identification of classes of functionally equivalent nodes in combinational circuits, based on OBDD comparison, is presented. To illustrate the methodology, the I/sub DDQ/ undetectable logic bridging faults have been identified in a set of benchmark circuits.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130265253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A new high level testability measure: description and evaluation 一种新的高级可测试性度量:描述与评价
Proceedings of IEEE VLSI Test Symposium Pub Date : 1994-04-25 DOI: 10.1109/VTEST.1994.292279
M. Gentil, D. Crestani, A. Rhalibi, C. Durante
{"title":"A new high level testability measure: description and evaluation","authors":"M. Gentil, D. Crestani, A. Rhalibi, C. Durante","doi":"10.1109/VTEST.1994.292279","DOIUrl":"https://doi.org/10.1109/VTEST.1994.292279","url":null,"abstract":"A high testability measure based on constraints propagation and dedicated to deterministic test of the combinational part of scannable circuits is compared to three others high level testability measures of the literature. This measure is used to guide hierarchical generation of test vectors and automatic test point insertion.<<ETX>>","PeriodicalId":111088,"journal":{"name":"Proceedings of IEEE VLSI Test Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123095375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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