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2015 IEEE International Memory Workshop (IMW)最新文献

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A Reliable Cross-Point MLC ReRAM with Sneak Current Compensation 具有潜流补偿的可靠的跨点MLC ReRAM
2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150272
J. Baek, Sang-Yun Kim, Jae-Koo Park, Jae-Young Park, K. Kwon
{"title":"A Reliable Cross-Point MLC ReRAM with Sneak Current Compensation","authors":"J. Baek, Sang-Yun Kim, Jae-Koo Park, Jae-Young Park, K. Kwon","doi":"10.1109/IMW.2015.7150272","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150272","url":null,"abstract":"In this paper, a reliable cross-point MLC ReRAM is introduced and fully integrated with 350nm CMOS technology. Both resistance states and variations are widely investigated with different compliance current. The self-termination scheme is adopted to prevent overstress to switched cell in set operation. As a result of self termination, write failure is prohibited and the uniformity on LRS of 300 uA compliance improved 2.3 times. In order to deter the compliance current offset in set operation, a sneak current compensation scheme of which controlled by ADC is proposed.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123835633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Technology Trends and Near-Future Applications of Embedded STT-MRAM 嵌入式STT-MRAM的技术趋势和近期应用
2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150308
S. Fujita, H. Noguchi, K. Ikegami, S. Takeda, K. Nomura, K. Abe
{"title":"Technology Trends and Near-Future Applications of Embedded STT-MRAM","authors":"S. Fujita, H. Noguchi, K. Ikegami, S. Takeda, K. Nomura, K. Abe","doi":"10.1109/IMW.2015.7150308","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150308","url":null,"abstract":"This paper presents fast and low-power embedded nonvolatile memory technologies and circuit designs based on perpendicular STT-MRAM. Future prospects of applications are also discussed.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114607914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Improved Lateral Coupling Cell for a Standard Logic Process eNVM Application 标准逻辑过程eNVM应用的改进横向耦合单元
2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150289
Kwang-il Choi, Nam-Yun Kim, Sung-Kun Park, I. Cho
{"title":"Improved Lateral Coupling Cell for a Standard Logic Process eNVM Application","authors":"Kwang-il Choi, Nam-Yun Kim, Sung-Kun Park, I. Cho","doi":"10.1109/IMW.2015.7150289","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150289","url":null,"abstract":"In this paper, we describe a new single poly MTP (multiple time programmable) cell using contact plate and select gate coupling manufactured by 90 nm standard CMOS (complementary metal-oxide semiconductor) process. Proposed MTP cell size is smaller than conventional well coupled MTP cell and only select gate lateral coupling MTP cell in order to have the similar coupling ratio (CR) as the 1.98~3.26 μm2. The program erase operation use channel hot electron injection (CHEI) and band to band hot hole injection (BTBT-HHI). The cell performances are compared with splits group by coupling ratio (CR). Through the results represented by the experiments, we were able to achieve cell endurance of 100 cycle and 10 year retention lifetime at 150 °C, and realize operation margin with ease if coupling ratio is increased by adding plate contact. The describing cell using coupling of select gate and plate contact is thought to have more useful application due to technology shrink.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132788124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Understanding NAND’s Intrinsic Characteristics Critical Role in Solid State Drive (SSD) Design 理解NAND的内在特性在固态硬盘(SSD)设计中的关键作用
2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150310
William E. Akin
{"title":"Understanding NAND’s Intrinsic Characteristics Critical Role in Solid State Drive (SSD) Design","authors":"William E. Akin","doi":"10.1109/IMW.2015.7150310","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150310","url":null,"abstract":"The use of NAND flash-based SSDs in enterprises has grown at a ~33% compound annual growth rate [1] worldwide for the past three years. The majority of the growth comes from enterprise data center applications where the trend is to leverage the cost benefits of using MLC and TLC NAND flash memory by focusing on the use model behavior to optimize performance and life characteristics. In the data center, requirements for these MLC/TLC SSDs demand high sequential performance and reliability, moderate IOPS, and low power consumption along with maintaining 3 to 5 years of useful life. These challenges are tackled by tightening the links between the SSD's operation, host operating environment, and intrinsic NAND memory behavior and by exploiting increasingly sophisticated controllers, firmware, and flash memory error management techniques.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133580534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Triple-Protection Structured COB FRAM with 1.2-V Operation and 1017-Cycle Endurance 一种具有1.2 v工作和1017循环寿命的三保护结构COB FRAM
2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150275
H. Saito, T. Sugimachi, Ko Nakamura, S. Ozawa, N. Sashida, S. Mihara, Y. Hikosaka, Wensheng Wang, Tomoyuki Hori, K. Takai, M. Nakazawa, N. Kosugi, M. Okuda, M. Hamada, S. Kawashima, T. Eshita, M. Matsumiya
{"title":"A Triple-Protection Structured COB FRAM with 1.2-V Operation and 1017-Cycle Endurance","authors":"H. Saito, T. Sugimachi, Ko Nakamura, S. Ozawa, N. Sashida, S. Mihara, Y. Hikosaka, Wensheng Wang, Tomoyuki Hori, K. Takai, M. Nakazawa, N. Kosugi, M. Okuda, M. Hamada, S. Kawashima, T. Eshita, M. Matsumiya","doi":"10.1109/IMW.2015.7150275","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150275","url":null,"abstract":"We have developed a ferroelectric RAM (FRAM) with a low operation voltage of 1.2 V and a high switching endurance up to 1017 cycles. Our newly developed triple-protection structured cell array, has constructed without an additional mask step, effectively protects 0.4-μm2 ferroelectric capacitors from hydrogen and moisture degradation. We have designed our capacitor-over-bit-line (COB) structure to have a small cell size of 0.5 μm2.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131930121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Dynamic Reference Sensing Scheme for Deeply Scaled STT-MRAM 深度缩放STT-MRAM的动态参考感知方案
2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150282
W. Kang, Tingting Pang, Youguang Zhang, D. Ravelosona, Weisheng Zhao
{"title":"Dynamic Reference Sensing Scheme for Deeply Scaled STT-MRAM","authors":"W. Kang, Tingting Pang, Youguang Zhang, D. Ravelosona, Weisheng Zhao","doi":"10.1109/IMW.2015.7150282","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150282","url":null,"abstract":"Spin transfer torque magnetic random access memory (STT-MRAM) has been considered as a potential candidate for the next-generation nonvolatile memory. However, as technology continuously scales down, the sensing margin (SM) of STT-MRAM is significantly degraded because of the increased process variations and reduced supply voltage. Meanwhile the critical switching current of magnetic tunnel junction (MTJ) also reduces with technology scaling. The sensing current, which should be limited to prevent read disturbance (RD) during read operations, further degrades the SM. Therefore, the readability becomes a new challenge for the deeply scaled STT-MRAM. To alleviate this problem, various sensing circuits and schemes have recently been proposed. However, it is rather difficult to achieve a good tradeoff among the sensing reliability, latency, power and hardware efficiency etc. This paper presents a dynamic reference cell (DRC) as well as a dynamic reference sensing (DRS) scheme to deal with this problem. Monte-Carlo statistical simulations have been performed to show the superiority of the proposed DRS scheme compared with conventional sensing schemes.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134171437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An Analytical Model of eMMC Key Performance Indicators eMMC关键绩效指标分析模型
2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150276
P. Amato, D. Caraccio, E. Confalonieri, M. Sforzin
{"title":"An Analytical Model of eMMC Key Performance Indicators","authors":"P. Amato, D. Caraccio, E. Confalonieri, M. Sforzin","doi":"10.1109/IMW.2015.7150276","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150276","url":null,"abstract":"Embedded Multi Media Card (eMMC) has become the mainstream embedded storage system for mobile devices like Smartphones and Tablets and it is gaining traction in other products (e.g. Wearables) and segments (e.g. Automotive). eMMC devices are complex embedded systems that include one or more Flash NAND chips and a microcontroller with a specific Firmware (FW). Estimating eMMC key performance indicators (KPIs) since the early stage of the product definition is paramount to identify potential gaps, and give prompt feedbacks to development teams. In this paper a sound theoretical framework for estimating eMMC system metrics is introduced. The mathematical model takes into account the most relevant architectural parameters of NANDs, microcontroller and FW.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117101336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Application Driven SCM and NAND Flash Hybrid SSD Design for Data-Centric Computing System 应用驱动的单片机和NAND闪存混合SSD数据中心计算系统设计
2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150277
Shun Okamoto, Chao Sun, Shogo Hachiya, Tomoaki Yamada, Yusuke Saito, T. Iwasaki, K. Takeuchi
{"title":"Application Driven SCM and NAND Flash Hybrid SSD Design for Data-Centric Computing System","authors":"Shun Okamoto, Chao Sun, Shogo Hachiya, Tomoaki Yamada, Yusuke Saito, T. Iwasaki, K. Takeuchi","doi":"10.1109/IMW.2015.7150277","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150277","url":null,"abstract":"In order to efficiently store, retrieve and process big data, the data-centric computing paradigm is adopted and an application-driven storage class memory (SCM)/NAND flash hybrid solid-state drive (SSD) is designed. SSD data management algorithms minimize data movement inside the storage system and the SSD system design parameter, SCM/NAND capacity ratio, is chosen depending on the application. Design guidelines are proposed, based on the evaluation of three SCM/NAND flash hybrid SSDs with: (1) write-back (WB) cache, (2) write-optimized data management (WO-DM) and (3) read-write balanced data management (RWB-DM) algorithms. The WO-DM algorithm achieves the highest SSD performance for write-intensive applications, whereas RWB-DM is most appropriate for read-hot (frequently accessed)-random workloads. As long as the workload is not read-cold-sequential or write-cold-sequential, adding SCM to the NAND SSD system is cost-effective to boost performance. Less than 10% SCM/NAND capacity ratios provides 10x speed, compared to the NAND flash-only SSD.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125735515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Novel Multi-Bit Non-Volatile SRAM Cells for Runtime Reconfigurable Computing 用于运行时可重构计算的新型多比特非易失SRAM单元
2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150297
Yanjun Ma
{"title":"Novel Multi-Bit Non-Volatile SRAM Cells for Runtime Reconfigurable Computing","authors":"Yanjun Ma","doi":"10.1109/IMW.2015.7150297","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150297","url":null,"abstract":"We discuss non-volatile SRAM cells capable of storing multiple bits and their applications as multi-context configuration memory. The cells are based on the standard 6T SRAM with multiple pairs of programmable resistors such as magnetic tunnel junction or resistive memory elements. In one of the cell designs the active state of the SRAM can be switched in one clock cycle by the use of an additional equalizer transistor, without the need to turn off the power to the cell, allowing real-time and low energy switching between different contexts in reconfigurable circuits. Other variations of the multistate non-volatile SRAM cells are also discussed.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122205658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Highly Reliable and Cost Effective 16nm Planar NAND Cell Technology 一种高可靠且低成本的16nm平面NAND电池技术
2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150269
William Kueber, G. Puzzilli, Niccolò Righetti, R. Basco, Lin Li, S. Beltrami, M. Bertuccio, E. Camozzi, David Daycock, Matthew King, Chris Larsen, Jeff Karpan, A. Goda, C. Roberts
{"title":"A Highly Reliable and Cost Effective 16nm Planar NAND Cell Technology","authors":"William Kueber, G. Puzzilli, Niccolò Righetti, R. Basco, Lin Li, S. Beltrami, M. Bertuccio, E. Camozzi, David Daycock, Matthew King, Chris Larsen, Jeff Karpan, A. Goda, C. Roberts","doi":"10.1109/IMW.2015.7150269","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150269","url":null,"abstract":"A 2D 16nm planar NAND cell technology is described with good cell to cell interference and reliability that can be used in a wide variety of applications. This second generation planar cell uses a high-K dielectric stack and a thin poly floating gate to maintain the needed gate coupling ratio and reduce adjacent cell interference. The technology includes select gates with the same planar structure as the cell. This select gate architecture simplifies the manufacturing of this NAND technology.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116854097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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