2015 IEEE International Memory Workshop (IMW)最新文献_第4页

A Reliable Cross-Point MLC ReRAM with Sneak Current Compensation 具有潜流补偿的可靠的跨点MLC ReRAM

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150272

J. Baek, Sang-Yun Kim, Jae-Koo Park, Jae-Young Park, K. Kwon

引用次数: 8

Technology Trends and Near-Future Applications of Embedded STT-MRAM 嵌入式STT-MRAM的技术趋势和近期应用

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150308

S. Fujita, H. Noguchi, K. Ikegami, S. Takeda, K. Nomura, K. Abe

引用次数: 10

Improved Lateral Coupling Cell for a Standard Logic Process eNVM Application 标准逻辑过程eNVM应用的改进横向耦合单元

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150289

Kwang-il Choi, Nam-Yun Kim, Sung-Kun Park, I. Cho

引用次数: 0

Understanding NAND’s Intrinsic Characteristics Critical Role in Solid State Drive (SSD) Design 理解NAND的内在特性在固态硬盘(SSD)设计中的关键作用

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150310

William E. Akin

引用次数: 2

A Triple-Protection Structured COB FRAM with 1.2-V Operation and 1017-Cycle Endurance 一种具有1.2 v工作和1017循环寿命的三保护结构COB FRAM

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150275

H. Saito, T. Sugimachi, Ko Nakamura, S. Ozawa, N. Sashida, S. Mihara, Y. Hikosaka, Wensheng Wang, Tomoyuki Hori, K. Takai, M. Nakazawa, N. Kosugi, M. Okuda, M. Hamada, S. Kawashima, T. Eshita, M. Matsumiya

引用次数: 3

Dynamic Reference Sensing Scheme for Deeply Scaled STT-MRAM 深度缩放STT-MRAM的动态参考感知方案

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150282

W. Kang, Tingting Pang, Youguang Zhang, D. Ravelosona, Weisheng Zhao

{"title":"Dynamic Reference Sensing Scheme for Deeply Scaled STT-MRAM","authors":"W. Kang, Tingting Pang, Youguang Zhang, D. Ravelosona, Weisheng Zhao","doi":"10.1109/IMW.2015.7150282","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150282","url":null,"abstract":"Spin transfer torque magnetic random access memory (STT-MRAM) has been considered as a potential candidate for the next-generation nonvolatile memory. However, as technology continuously scales down, the sensing margin (SM) of STT-MRAM is significantly degraded because of the increased process variations and reduced supply voltage. Meanwhile the critical switching current of magnetic tunnel junction (MTJ) also reduces with technology scaling. The sensing current, which should be limited to prevent read disturbance (RD) during read operations, further degrades the SM. Therefore, the readability becomes a new challenge for the deeply scaled STT-MRAM. To alleviate this problem, various sensing circuits and schemes have recently been proposed. However, it is rather difficult to achieve a good tradeoff among the sensing reliability, latency, power and hardware efficiency etc. This paper presents a dynamic reference cell (DRC) as well as a dynamic reference sensing (DRS) scheme to deal with this problem. Monte-Carlo statistical simulations have been performed to show the superiority of the proposed DRS scheme compared with conventional sensing schemes.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134171437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Optimization of Ru Based Hybrid Floating Gate for Planar NAND Flash 平面NAND闪存中Ru基混合浮栅的优化设计

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150298

L. Breuil, J. Lisoni, P. Blomme, G. Van den bosch, J. van Houdt

引用次数: 2

Efficiently Realizing Weak Cell Aware DRAM Error Tolerance for Sub-20nm Technology Nodes 有效实现亚20nm节点弱单元感知DRAM容错

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150283

Hao Wang, Kai Zhao, Tong Zhang

{"title":"Efficiently Realizing Weak Cell Aware DRAM Error Tolerance for Sub-20nm Technology Nodes","authors":"Hao Wang, Kai Zhao, Tong Zhang","doi":"10.1109/IMW.2015.7150283","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150283","url":null,"abstract":"DRAM industry faces a grand challenge on continuing the scaling of storage node aspect ratio (A/R) to maintain the storage node storage capacitance. One viable option is to intentionally slow down the A/R scaling at the penalty of irreparable weak cells that cannot guarantee target data retention time under worst-case scenarios, and compensate the weak-cell-induced memory errors at the system level. Although the availability of weak cell location information can be leveraged to maximize the weak-cell-induced error tolerance, a straightforward realization of weak cell aware error tolerance tends to suffer from significant memory access latency overhead, especially in the presence of a large number of weak cells. This paper presents a design solution that can realize weak cell aware error tolerance at very small memory access latency overhead. The key is to use a hybrid error detection/correction process to eliminate unnecessary access to the weak cell location information. We carried out extensive simulations and evaluations to demonstrate the effectiveness of this design solution and the trade-offs. Beyond theoretical analysis on the latency overhead, we further performed full-system simulations based upon a cycle-accurate x86 simulator and DRAM simulation, and implemented our design solution using an FPGA development board with on-board DRAM chips. The results successfully show that our design solution can readily handle the weak-cell-induced memory error rate of upto 10-4 ~ 10-3 at very small (even negligible) latency overhead.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130793891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Novel Multi-Bit Non-Volatile SRAM Cells for Runtime Reconfigurable Computing 用于运行时可重构计算的新型多比特非易失SRAM单元

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150297

Yanjun Ma

引用次数: 1

Optimization of TiN/TaOx/HfO2/TiN RRAM Arrays for Improved Switching and Data Retention 优化TiN/TaOx/HfO2/TiN RRAM阵列以改善交换和数据保留

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150300

Xueyao Huang, Huaqiang Wu, D. Sekar, S. Nguyen, Kun Wang, H. Qian

引用次数: 20