2015 IEEE International Memory Workshop (IMW)最新文献_第2页

A Study of Blocking and Tunnel Oxide Engineering on Double-Trapping (DT) BE-SONOS Performance 双捕集(DT) BE-SONOS性能的阻塞和隧道氧化工程研究

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150273

R. Lo, P. Du, T. Hsu, C. Wu, Jung-Yi Guo, C. Cheng, H. Lue, Y. Shih, T. Hou, K. Hsieh, Chih-Yuan Lu

{"title":"A Study of Blocking and Tunnel Oxide Engineering on Double-Trapping (DT) BE-SONOS Performance","authors":"R. Lo, P. Du, T. Hsu, C. Wu, Jung-Yi Guo, C. Cheng, H. Lue, Y. Shih, T. Hou, K. Hsieh, Chih-Yuan Lu","doi":"10.1109/IMW.2015.7150273","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150273","url":null,"abstract":"Double-trapping bandgap engineered SONOS (DT BE-SONOS) [1] was proposed to provide both fast erase speed and deep erase by means of a second nitride trapping layer and an additional blocking oxide on top of BE-SONOS. Although this provides excellent erase performance but the additional layers increase the EOT and subsequently the erase voltage, thus it is desirable to minimize their impact. This work investigates exhaustively the effect of thinning down the blocking layers. Since the ISPP and high temperature retention charge loss are mainly dominated by the ONO thickness of BE-SONOS below the blocking layers, reducing the blocking layer thickness has only minor impact on ISPP and retention. Moreover, erase saturation is determined by the dynamic balance of channel hole injection and gate electron injection. Experimental data show that reducing the thickness of the oxide between two trapping layers has little impact on erase saturation once the gate injected electrons are efficiently suppressed by the top most oxide. We have also investigated retention improvement by various oxides. By using HQ-SiO2 to replace the top tunnel ONO the trapped electron out-tunneling is reduced. Thus retention may be improved without increasing the effective oxide thickness.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121839995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Comprehensive Methodology for ReRAM and Selector Design Guideline of Cross-point Array 交叉点阵列的ReRAM综合方法及选择器设计准则

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150280

Sangheon Lee, Sooeun Lee, Kibong Moon, Jaehyuk Park, Byungsub Kim, H. Hwang

引用次数: 8

TCAD Simulation of Data Retention Characteristics of Charge Trap Device for 3-D NAND Flash Memory 三维NAND闪存电荷阱器件数据保持特性的TCAD仿真

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150306

Dongyean Oh, Bonghoon Lee, Eunmee Kwon, Sangyong Kim, G. Cho, Sungkye Park, Seokkiu Lee, Sungjoo Hong

引用次数: 18

Universal Thermoelectric Characteristic in Phase Change Memories 相变存储器中的通用热电特性

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150311

N. Ciocchini, M. Laudato, A. Leone, P. Fantini, A. Lacaita, D. Ielmini

引用次数: 2

Relationship among Current Fluctuations during Forming, Cell-To-Cell Variability and Reliability in RRAM Arrays RRAM阵列形成过程中电流波动、单元间变异性和可靠性的关系

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150303

A. Grossi, C. Zambelli, P. Olivo, E. Miranda, V. Stikanov, T. Schroeder, C. Walczyk, C. Wenger

引用次数: 22

From Resistive Switching Mechanisms in AM4Q8 Mott Insulators to Mott Memories 从AM4Q8莫特绝缘体的电阻开关机制到莫特存储器

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150287

J. Tranchant, E. Janod, B. Corraze, M. Besland, L. Cario

引用次数: 0

Performance Prediction of Large-Scale 1S1R Resistive Memory Array Using Machine Learning 基于机器学习的大规模1S1R阻性存储阵列性能预测

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150302

Zizhen Jiang, Peng Huang, Liang Zhao, Shahar Kvatinsky, Shimeng Yu, Xiaoyan Liu, Jinfeng Kang, Y. Nishi, H. Wong

引用次数: 12

A 16-Level-Cell Nonvolatile Memory with Crystalline In-Ga-Zn Oxide FET 一种具有晶体In-Ga-Zn氧化场效应晶体管的16电平电池非易失性存储器

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150266

T. Matsuzaki, T. Onuki, S. Nagatsuka, H. Inoue, T. Ishizu, Y. Ieda, Naoto Yamade, H. Miyairi, M. Sakakura, Y. Shionoiri, K. Kato, T. Okuda, J. Koyama, Yoshitaka Yamamoto, S. Yamazaki

引用次数: 2

Functionality Demonstration of a High-Density 1.1V Self-Aligned Split-Gate NVM Cell Embedded into LP 40 nm CMOS for Automotive and Smart Card Applications 用于汽车和智能卡应用的高密度1.1V自对准分栅NVM单元嵌入LP 40 nm CMOS的功能演示

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150288

L. Luo, Y. Chow, X. Cai, F. Zhang, Z. Teo, D. Wang, K. Lim, B. Zhou, J. F. Liu, A. Yeo, T. Chang, Y. Kong, C. W. Yap, S. Lup, R. Long, J. B. Tan, D. Shum, N. Do, J. Kim, P. Ghazavi, V. Tiwari

{"title":"Functionality Demonstration of a High-Density 1.1V Self-Aligned Split-Gate NVM Cell Embedded into LP 40 nm CMOS for Automotive and Smart Card Applications","authors":"L. Luo, Y. Chow, X. Cai, F. Zhang, Z. Teo, D. Wang, K. Lim, B. Zhou, J. F. Liu, A. Yeo, T. Chang, Y. Kong, C. W. Yap, S. Lup, R. Long, J. B. Tan, D. Shum, N. Do, J. Kim, P. Ghazavi, V. Tiwari","doi":"10.1109/IMW.2015.7150288","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150288","url":null,"abstract":"This paper successfully demonstrates a functional and reliable self-aligned, split-gate NVM cell, down to a very competitive and small cell size. This NVM cell is embedded into a 40 nm Low Power (LP) ground rule logic process with copper low-K interconnects. The self- alignment sequence with gate spacer and poly CMP (Chemical Mechanical Polishing) provides an optimized and small cell that can be easily integrated in the standard logic process, in a modular way. This is the first time that the industry has demonstrated a functional split-gate embedded Flash memory cell at 1.1V VDD. This embedded Flash process also yielded on a baseline 32 Mb high-density SRAM test chip as well as a 10% larger automotive-grade embedded Flash cell. We have further demonstrated reliability data that met the tightest market requirements, with a more relaxed 55 nm ground rule on a 16 Mb test array, using the same 40 nm LP process.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128840365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Characterization and Modeling of Advanced Placement Algorithms for NAND Flash Arrays NAND闪存阵列先进放置算法的表征与建模

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI: 10.1109/IMW.2015.7150279

C. Miccoli, K. Sarpatwari, Domenico Di Cicco, Mattia Cichocki, V. Moschiano, P. Ruby, K. Parat

引用次数: 0