Functionality Demonstration of a High-Density 1.1V Self-Aligned Split-Gate NVM Cell Embedded into LP 40 nm CMOS for Automotive and Smart Card Applications

Abstract

This paper successfully demonstrates a functional and reliable self-aligned, split-gate NVM cell, down to a very competitive and small cell size. This NVM cell is embedded into a 40 nm Low Power (LP) ground rule logic process with copper low-K interconnects. The self- alignment sequence with gate spacer and poly CMP (Chemical Mechanical Polishing) provides an optimized and small cell that can be easily integrated in the standard logic process, in a modular way. This is the first time that the industry has demonstrated a functional split-gate embedded Flash memory cell at 1.1V VDD. This embedded Flash process also yielded on a baseline 32 Mb high-density SRAM test chip as well as a 10% larger automotive-grade embedded Flash cell. We have further demonstrated reliability data that met the tightest market requirements, with a more relaxed 55 nm ground rule on a 16 Mb test array, using the same 40 nm LP process.