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Reconfigurable Germanium Quantum-Dot Arrays for CMOS Integratable Quantum Electronic Devices 用于CMOS可积量子电子器件的可重构锗量子点阵列
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492360
I-Hsiang Wang, T. Tsai, R. Pan, P. Hong, M. Kuo, I. Chen, T. George, H. Lin, Pei-Wen Li
{"title":"Reconfigurable Germanium Quantum-Dot Arrays for CMOS Integratable Quantum Electronic Devices","authors":"I-Hsiang Wang, T. Tsai, R. Pan, P. Hong, M. Kuo, I. Chen, T. George, H. Lin, Pei-Wen Li","doi":"10.23919/VLSICircuits52068.2021.9492360","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492360","url":null,"abstract":"We report the first-of-kind scalability and tunability of Ge QDs that are controllably sized, closely coupled, and self-aligned with control gates, using a combination of lithographic patterning, spacer technology, and self-assembled growth. The core experimental design is based on the thermal oxidation of poly-SiGe spacer islands designated at each included-angle location of designed Si3N4/c-Si ridge structures. Multiple Ge QDs with good size tunability of 7–20 nm were controllably achieved by adjusting the process times for deposition, etch back and thermal oxidation of poly-SiGe spacer islands. Our Ge QDs array provides a common platform for engineering diverse QD electronic devices with desired reconfigurability and optimizing their performance.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122966167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 0.6V 86.5dB-DR 40kHz-BW Inverter-Based Continuous-Time Delta-Sigma Modulator with PVT-Robust Body-Biasing Technique 基于pvt鲁棒体偏置技术的0.6V 86.5dB-DR 40kHz-BW逆变器连续δ - sigma调制器
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492519
Sangwoo Lee, Sungsik Park, Yunhong Kim, Youngcheol Chae
{"title":"A 0.6V 86.5dB-DR 40kHz-BW Inverter-Based Continuous-Time Delta-Sigma Modulator with PVT-Robust Body-Biasing Technique","authors":"Sangwoo Lee, Sungsik Park, Yunhong Kim, Youngcheol Chae","doi":"10.23919/VLSICircuits52068.2021.9492519","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492519","url":null,"abstract":"This paper presents a body-biasing technique for an energy-efficient inverter-based integrator that significantly improves the PVT robustness of the integrators in sub-1V continuous-time delta-sigma modulators (CTDSMs). A prototype CTDSM with the body-biasing technique is implemented in a 28 nm CMOS process and achieves 83 dB SNDR, 84 dB SNR, and 86.5 dB DR in a 40-kHz bandwidth, while consuming only 33.6 μW from a 0.6 V supply. It achieves a Schreier FoM of 177.3 dB.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116773079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference CHIMERA:一个0.92 TOPS, 2.2 TOPS/W Edge AI加速器，带有2 MByte片上代工厂电阻式RAM，用于高效的训练和推理
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492347
M. Giordano, Kartik Prabhu, Kalhan Koul, R. Radway, Albert Gural, Rohan Doshi, Zainab F. Khan, John W. Kustin, Timothy Liu, Gregorio B. Lopes, Victor Turbiner, W. Khwa, Y. Chih, Meng-Fan Chang, Guénolé Lallement, B. Murmann, S. Mitra, Priyanka Raina
{"title":"CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference","authors":"M. Giordano, Kartik Prabhu, Kalhan Koul, R. Radway, Albert Gural, Rohan Doshi, Zainab F. Khan, John W. Kustin, Timothy Liu, Gregorio B. Lopes, Victor Turbiner, W. Khwa, Y. Chih, Meng-Fan Chang, Guénolé Lallement, B. Murmann, S. Mitra, Priyanka Raina","doi":"10.23919/VLSICircuits52068.2021.9492347","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492347","url":null,"abstract":"CHIMERA is the first non-volatile deep neural network (DNN) chip for edge AI training and inference using foundry on-chip resistive RAM (RRAM) macros and no off-chip memory. CHIMERA achieves 0.92 TOPS peak performance and 2.2 TOPS/W. We scale inference to 6x larger DNNs by connecting 6 CHIMERAs with just 4% execution time and 5% energy costs, enabled by communication-sparse DNN mappings that exploit RRAM non-volatility through quick chip wakeup/shutdown (33 µs). We demonstrate the first incremental edge AI training which overcomes RRAM write energy, speed, and endurance challenges. Our training achieves the same accuracy as traditional algorithms with up to 283x fewer RRAM weight update steps and 340x better energy-delay product. We thus demonstrate 10 years of 20 samples/minute incremental edge AI training on CHIMERA.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132288939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
A Cost-Effective On-Chip Power Impedance Measurement (PIM) System in 7nm FinFET for HPC Applications 用于高性能计算的7nm FinFET片上功率阻抗测量(PIM)系统
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492470
T. Lu, Chin-Ming Fu, Chia-Chun Liao, Yu-Tso Lin, Chih-Hsien Chang, K. Hsieh
{"title":"A Cost-Effective On-Chip Power Impedance Measurement (PIM) System in 7nm FinFET for HPC Applications","authors":"T. Lu, Chin-Ming Fu, Chia-Chun Liao, Yu-Tso Lin, Chih-Hsien Chang, K. Hsieh","doi":"10.23919/VLSICircuits52068.2021.9492470","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492470","url":null,"abstract":"This work shows a system for power delivery network (PDN) impedance measurements (PIM), targeting high-performance computing (HPC) applications. A delay-line based \"TRIG-after-SAMP\" approach relaxes timing margins and eliminates high-speed clock sources. On-chip DUTs, with two bonding schemes and a programmable de-coupling capacitor array, are demonstrated using 7nm FinFET technology. Measurement results show that this system achieves a sampling bandwidth of 27 GHz, an accuracy of 1 mV, and a core area of 0.028 mm2.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134256480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC 一种辅助信道共享的背景失真和增益校准方法，在1GS/s ADC中实现4奈奎斯特区80db SFDR改善
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492336
Lai Wei, Zihao Zheng, N. Markulić, J. Lagos, E. Martens, Yan Zhu, Chi-Hang Chan, J. Craninckx, R. Martins
{"title":"An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC","authors":"Lai Wei, Zihao Zheng, N. Markulić, J. Lagos, E. Martens, Yan Zhu, Chi-Hang Chan, J. Craninckx, R. Martins","doi":"10.23919/VLSICircuits52068.2021.9492336","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492336","url":null,"abstract":"This paper presents an auxiliary-channel-assisted background calibration for ADC’s input front-end (buffer + T/H) distortion and inter-stage gain error. The auxiliary channel is custom-designed which runs at a fractional speed of the main ADC with only moderate noise performance but high linearity. It also has a pseudo inter-stage gain characteristic as the main ADC, which incorporates with the multi-layer LMS procedure, facilitating a fast convergence speed. Verified in a 12-bit 1GS/s pipelined SAR ADC in 28nm CMOS, the SNDR and SFDR at Nyquist input are 59.28 dB and 67.09 dB SFDR, respectively. Just the distortion calibrations alone contribute >11.13dB SFDR improvement in the entire Nyquist band. Both the ADCs and input buffers work under a 1V supply, consuming 19.2mW with 17% from the buffer.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134495089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1070 pJ/b 169 Mb/s Quad-core Digital Baseband SoC for Distributed and Cooperative Massive MIMO in 28 nm FD-SOI 一种1070 pJ/b 169mb /s四核数字基带SoC，用于28nm FD-SOI中分布式和协作式大规模MIMO
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492455
H. Prabhu, Liang Liu, F. Sheikh, O. Edfors
{"title":"A 1070 pJ/b 169 Mb/s Quad-core Digital Baseband SoC for Distributed and Cooperative Massive MIMO in 28 nm FD-SOI","authors":"H. Prabhu, Liang Liu, F. Sheikh, O. Edfors","doi":"10.23919/VLSICircuits52068.2021.9492455","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492455","url":null,"abstract":"A 2.2 mm2 full digital baseband SoC with four heterogeneous cores for 128-node 8-users distributed massive MIMO is presented. Two specialized DSPs perform rapid over-the-air synchronization within 0.1ms. A highly optimized 8-complex lane MIMO vector processor provides 4x hardware efficiency improvement over general-purpose processors. Circuit optimizations and the use of body-bias result in 1070 pJ/b measured energy at 169 Mb/s detection rate.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115139839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference 基于片上深度神经网络推理的34mb可编程内存计算加速器
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492403
Shihui Yin, Bo Zhang, Minkyu Kim, Jyotishman Saikia, Soon-Chan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Mingoo Seok, Jae-sun Seo
{"title":"PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference","authors":"Shihui Yin, Bo Zhang, Minkyu Kim, Jyotishman Saikia, Soon-Chan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Mingoo Seok, Jae-sun Seo","doi":"10.23919/VLSICircuits52068.2021.9492403","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492403","url":null,"abstract":"We present a programmable in-memory computing (IMC) accelerator integrating 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 Mb, demonstrating one of the largest IMC hardware to date. We developed a custom ISA featuring IMC and SIMD functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28nm prototype chip achieves system-level peak energy-efficiency of 437 TOPS/W and peak throughput of 4.9 TOPS at 40MHz, 1V supply.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"17 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113970775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 10A/μs Fast Transient AOT Voltage Regulator on DDR5 DIMM with Dithered Pseudo-Constant Switching Frequency Achieving -6dB Harmonic Suppression 基于DDR5伪恒定开关频率抖动的10A/μs快速瞬态AOT稳压器实现-6dB谐波抑制
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492332
Taeyoung Chung, Sooa Kim, Jehyung Yoon, Hee-Min Han, K. Park, Hokyu Lee, Ho-Young Yoon, Sun-Kyu Lee, Jongyoon Lim, Yongjin Kwon, Jungbong Lee, Sung-Ung Kwak
{"title":"A 10A/μs Fast Transient AOT Voltage Regulator on DDR5 DIMM with Dithered Pseudo-Constant Switching Frequency Achieving -6dB Harmonic Suppression","authors":"Taeyoung Chung, Sooa Kim, Jehyung Yoon, Hee-Min Han, K. Park, Hokyu Lee, Ho-Young Yoon, Sun-Kyu Lee, Jongyoon Lim, Yongjin Kwon, Jungbong Lee, Sung-Ung Kwak","doi":"10.23919/VLSICircuits52068.2021.9492332","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492332","url":null,"abstract":"The on-board voltage regulator in the DDR5 memory module is required to resiliently supply current at large load transient events and alleviate output noise at the same time. We present an adaptive on-time (AOT) buck regulator with a turbo dual-phase interleaving logic for stable regulation and on-time control with dithered pseudo-constant switching frequency to suppress output harmonics by 6dB. The voltage regulator delivers up to 10A with a peak efficiency of 92.5% and covers 10A/μs steep load transients.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126219964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration 20GS/s 8b时域交错ADC与输入无关的背景时间倾斜校准
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492436
Minglei Zhang, Yan Zhu, Chi-Hang Chan, R. Martins
{"title":"A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration","authors":"Minglei Zhang, Yan Zhu, Chi-Hang Chan, R. Martins","doi":"10.23919/VLSICircuits52068.2021.9492436","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492436","url":null,"abstract":"This paper demonstrates a background timing skew calibration for the time-interleaved (TI) ADCs using a direct time-based estimation to facilitate the input-independent and fast convergence features. It suppresses the timing spurs of a 20GS/s 8× TI-ADC below ‒50dB at a Nyquist input regardless of the calibrating input condition with 24 calibration cycles. The 8b time-domain TI-ADC achieves a 91.3fJ/conv.-step FoMWalden and >16GHz bandwidth.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122354956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 5.5mW/Channel 2-to-7 GHz Frequency Synthesizable Qubit-Controlling Cryogenic Pulse Modulator for Scalable Quantum Computers 用于可扩展量子计算机的5.5mW/通道2- 7 GHz频率合成量子比特低温脉冲调制器
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492343
K. Kang, Byungjun Kim, Gahyun Choi, Sun-Kyung Lee, Jisoo Choi, Jaeho Lee, Seokhyeong Kang, Moonjoo Lee, Ho-Jin Song, Y. Chong, J. Sim
{"title":"A 5.5mW/Channel 2-to-7 GHz Frequency Synthesizable Qubit-Controlling Cryogenic Pulse Modulator for Scalable Quantum Computers","authors":"K. Kang, Byungjun Kim, Gahyun Choi, Sun-Kyung Lee, Jisoo Choi, Jaeho Lee, Seokhyeong Kang, Moonjoo Lee, Ho-Jin Song, Y. Chong, J. Sim","doi":"10.23919/VLSICircuits52068.2021.9492343","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492343","url":null,"abstract":"This work presents a qubit controller IC based on the direct synthesis. The IC consists of six independently-working pulse modulators utilizing the same LO frequency. We propose a sinusoid-shaping nonlinear DAC followed by a linear interpolating DAC to improve both of energy and hardware efficiencies. The implemented IC in 40nm CMOS is verified by superconducting qubit operations with Rabi and Ramsey oscillations while consuming power of < 1/60 compared with the previous state-of-the-art.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125722891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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