T. Lu, Chin-Ming Fu, Chia-Chun Liao, Yu-Tso Lin, Chih-Hsien Chang, K. Hsieh
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A Cost-Effective On-Chip Power Impedance Measurement (PIM) System in 7nm FinFET for HPC Applications
This work shows a system for power delivery network (PDN) impedance measurements (PIM), targeting high-performance computing (HPC) applications. A delay-line based "TRIG-after-SAMP" approach relaxes timing margins and eliminates high-speed clock sources. On-chip DUTs, with two bonding schemes and a programmable de-coupling capacitor array, are demonstrated using 7nm FinFET technology. Measurement results show that this system achieves a sampling bandwidth of 27 GHz, an accuracy of 1 mV, and a core area of 0.028 mm2.
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