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Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97最新文献

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The importance of interfaces: a HW/SW codesign case study 接口的重要性:一个硬件/软件协同设计案例研究
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584584
D. Jensen, J. Madsen, Steen Pedersen
{"title":"The importance of interfaces: a HW/SW codesign case study","authors":"D. Jensen, J. Madsen, Steen Pedersen","doi":"10.1109/HSC.1997.584584","DOIUrl":"https://doi.org/10.1109/HSC.1997.584584","url":null,"abstract":"This paper presents a codesign case study in image analysis. The main objective is to stress the importance of handling HW/SW interfaces more precisely at the system level. In the presented case study, there is an intuitive and simple HW/SW interface, which is based upon the functional modules in the application. However, it is found that this seemingly sound choice caused a number of practical problems and sub-optimal solutions during the implementation of the prototype system.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"89 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129743958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
An approach to mixed systems co-synthesis 混合系统协同合成的一种方法
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584572
T. Benner, R. Ernst
{"title":"An approach to mixed systems co-synthesis","authors":"T. Benner, R. Ernst","doi":"10.1109/HSC.1997.584572","DOIUrl":"https://doi.org/10.1109/HSC.1997.584572","url":null,"abstract":"The paper presents an extension of co-synthesis for data dominated applications to include reactive processes. The extension allows for rate constraints as used in data dominated applications as well as minimum and maximum time constraints for communication and I/O which is required to define reactive behavior of control tasks. A co-synthesis approach is proposed which differentiates global process and communication scheduling, which is non preemptive, and local scheduling which includes a restricted interrupt controlled process invocation to extend the design space. Several user parameters allow design space exploration. The approach includes buffering, process pipelining and parallelization for control as well as for data dominated tasks on different levels of granularity. It supports inter process time constraints which span processes with different periods. The target architectures are heterogeneous systems consisting of multiple processors, hardware components, memories and different types of communication media.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125947111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Modeling micro-controller peripherals for high-level co-simulation and synthesis 为高级联合仿真和综合建模微控制器外设
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584591
H. Hsieh, A. Sangiovanni-Vincentelli
{"title":"Modeling micro-controller peripherals for high-level co-simulation and synthesis","authors":"H. Hsieh, A. Sangiovanni-Vincentelli","doi":"10.1109/HSC.1997.584591","DOIUrl":"https://doi.org/10.1109/HSC.1997.584591","url":null,"abstract":"Mapping the behavior on an embedded system involves hardware-software partitioning and assignment of software and hardware tasks to different components. In particular, software tasks in embedded controllers are mostly assigned to a micro-controller. However, some micro-controller peripherals are implemented with partly programmable components that can be regarded as very simple co-processors with limited instruction sets and capabilities. Embedded system designers are used for mapping some simple software tasks onto these simple co-processors, obtaining overall performances that can be orders of magnitude superior to the ones obtained mapping all software tasks to the microcontroller itself. We propose a methodology to specify, simulate, and partition tasks that can be implemented on programmable micro-controller peripherals such as timing processing units (TPUs). Following our general philosophy, we let the designer propose a partition, and we provide an environment: to efficiently simulate and evaluate a particular implementation choice; and to automate downstream synthesis for software, hardware, as well as peripheral programming routines.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126758781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An event-driven multi-threading architecture for embedded systems 用于嵌入式系统的事件驱动多线程体系结构
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584575
R. Gerndt, R. Ernst
{"title":"An event-driven multi-threading architecture for embedded systems","authors":"R. Gerndt, R. Ernst","doi":"10.1109/HSC.1997.584575","DOIUrl":"https://doi.org/10.1109/HSC.1997.584575","url":null,"abstract":"In this paper we present an event driven multi-threading architecture and its underlying event flow system model of computation as a framework for the implementation of complex reactive and communication systems. Existing process oriented specification languages can be used to specify the system and embedded in the model. The target architecture covers a wide variety of architectures, varying from small FSMs to large processors, which are interconnected by a network template which performs dynamic scheduling and communication for different levels of process granularity and timing. Interconnect and module implementation and optimisation is based on an event flow graph model (EFG). In this paper we present our system model and the architectural template and show how they can be applied to an industrial application example.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125722759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Interface optimization during hardware-software partitioning 硬件软件分区期间的接口优化
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584582
L. Freund, D. Dupont, M. Israël, F. Rousseau
{"title":"Interface optimization during hardware-software partitioning","authors":"L. Freund, D. Dupont, M. Israël, F. Rousseau","doi":"10.1109/HSC.1997.584582","DOIUrl":"https://doi.org/10.1109/HSC.1997.584582","url":null,"abstract":"We present an approach allowing communication optimization during the hardware-software partitioning task. Our methodology focuses on systems represented by a dataflow graph whose nodes are elements of libraries. To abstract the communication constraints, we include communication nodes in this graph. Consequently assignment and scheduling of communications and operations can be determined together by the same partitioning algorithm. During partitioning, protocol optimization and bus scheduling are realized. We illustrate with a telecommunication system example the feasibility and the usefulness of our methodology.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124870828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Communication synthesis for embedded systems with global considerations 具有全局考虑的嵌入式系统通信综合
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584581
R. Ortega, G. Borriello
{"title":"Communication synthesis for embedded systems with global considerations","authors":"R. Ortega, G. Borriello","doi":"10.1109/HSC.1997.584581","DOIUrl":"https://doi.org/10.1109/HSC.1997.584581","url":null,"abstract":"Designers of distributed embedded systems require communication synthesis to more effectively explore the design space. Communication synthesis creates or instantiates the necessary software and hardware required to allow system components to exchange data. This work examines the problem of mapping a high-level specification to an arbitrary, but fixed architecture that uses particular bus protocols for interprocessor communication. The approach detailed in this paper illustrates that global considerations are necessary to achieve a correct implementation. A communication model is presented that allows for easy retargeting to different bus topologies and protocols. The effectiveness of this approach is demonstrated by mapping a high-level specification to different architectures.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122420423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Software acceleration using coprocessors: is it worth the effort? 使用协处理器的软件加速:值得吗?
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584592
M. Edwards
{"title":"Software acceleration using coprocessors: is it worth the effort?","authors":"M. Edwards","doi":"10.1109/HSC.1997.584592","DOIUrl":"https://doi.org/10.1109/HSC.1997.584592","url":null,"abstract":"A commonly accepted technique in hardware/software co-design is to implement as many system functions as possible in software and to move performance-critical functions into special-purpose external hardware in order to either satisfy timing constraints or reduce the overall execution time of a program-this is known as \"software acceleration\". This paper investigates the limits to the performance enhancements obtainable using software acceleration techniques. A practical target architecture, based on the use of programmable logic, is used to illustrate the problems associated with software acceleration. It is shown that, normally, little benefit can be obtained by applying software acceleration methods to general-purpose applications. Whereas software acceleration can profitably be used in a limited number of special-purpose applications, a designer would probably be better off developing ASIP (application-specific instruction-set processor) components, based on heterogeneous multiprocessor architectures.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115912234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Design-for-debug in hardware/software co-design 硬件/软件协同设计中的为调试而设计
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584576
H. Vranken, M. Stevens, M. Segers
{"title":"Design-for-debug in hardware/software co-design","authors":"H. Vranken, M. Stevens, M. Segers","doi":"10.1109/HSC.1997.584576","DOIUrl":"https://doi.org/10.1109/HSC.1997.584576","url":null,"abstract":"The increasing complexity of hardware/software systems is handled effectively by hardware/software codesign methods. However, the debugging of hardware/software systems is still a very troublesome process. This is mainly due to the limited accessibility to the internals of embedded hardware/software systems. Debugging is also hindered by the nature of the design errors encountered during hardware/software debugging. We present a structured design-for-debug strategy to address the problems of hardware/software debugging. Our design-for-debug strategy is an integral part of hardware/software codesign. Furthermore, we re-use the hardware design-for-test-facilities to reduce the overhead costs of design-for-debug. Two examples are provided to illustrate our design-for-debug strategy.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122641386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A flexible model for evaluating the behavior of hardware/software systems 用于评估硬件/软件系统行为的灵活模型
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584588
A. Allara, S. Filipponi, F. Salice, W. Fornaciari, D. Sciuto
{"title":"A flexible model for evaluating the behavior of hardware/software systems","authors":"A. Allara, S. Filipponi, F. Salice, W. Fornaciari, D. Sciuto","doi":"10.1109/HSC.1997.584588","DOIUrl":"https://doi.org/10.1109/HSC.1997.584588","url":null,"abstract":"Hardware-software co-design is becoming a \"must\" for many embedded applications requiring to tradeoff a number of constraints such as size, cost, performance, real-time requirements, design flexibility, etc. Even if, according to the purpose of the digital system, the range of possible architectures is rather wide, for our field of interest (telecom embedded systems) the target architecture can be roughly described as composed of a microprocessor surrounded by some hardware modules connected through buses. The aim of this paper is to present a model (and the related CAD environment) supporting the simultaneous analysis of functionality, timing performance (in terms of execution time of hw and sw modules and bus use), and execution profile of the system specification assuming the given target architecture. The goal of the proposed approach has been to define a simulation algorithm able to consider the partition of each section of the specification and the consequent bus traffic at the system level, in order to enable the designer to efficiently debug and evaluate the specification while considering the timing issues of a mixed hw-sw architecture very close to the final one. The paper gives also the flavor of the CAD environment built around the presented simulation strategy.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127344234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A hardware/software codesign method for a general purpose reconfigurable co-processor 一种通用可重构协处理器的硬件/软件协同设计方法
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584594
S. Kimura, Y. Itou, M. Hirao, Katsumasa Watanabe, M. Yukishita, A. Nagoya
{"title":"A hardware/software codesign method for a general purpose reconfigurable co-processor","authors":"S. Kimura, Y. Itou, M. Hirao, Katsumasa Watanabe, M. Yukishita, A. Nagoya","doi":"10.1109/HSC.1997.584594","DOIUrl":"https://doi.org/10.1109/HSC.1997.584594","url":null,"abstract":"Shows a hardware/software codesign method for a computer system with a reconfigurable co-processor. The reconfigurable co-processor is constructed from FPGAs, internal cache and a control part, and is connected to the system bus of the computer system. This paper shows the architecture of the reconfigurable co-processor, a hardware/software separation method and a co-operation method via DMA-based memory sharing. We also show co-operation examples and the effectiveness of our approach for the fast execution of user processes.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116782323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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