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Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97最新文献

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Architecture synthesis and partitioning of real-time systems: a comparison of three heuristic search strategies 实时系统的架构综合与划分:三种启发式搜索策略的比较
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584596
J. Axelsson
{"title":"Architecture synthesis and partitioning of real-time systems: a comparison of three heuristic search strategies","authors":"J. Axelsson","doi":"10.1109/HSC.1997.584596","DOIUrl":"https://doi.org/10.1109/HSC.1997.584596","url":null,"abstract":"Studies the problem of automatically selecting a suitable system architecture for implementing a real-time application. Given a library of hardware components, it is shown how an architecture can be synthesized with the goal of fulfilling the real-time constraints stated in the system's specification. In the case where the selected architecture contains several processing units, the specification is partitioned by assigning tasks to these. The use of three heuristic search techniques is investigated: genetic algorithms, simulated annealing and tabu search; and it is described how these can be adapted to the architecture synthesis problem. It is concluded that tabu search is the most promising technique but that simulated annealing is also applicable.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115169600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
Performance analysis in CoDe-X partitioning for structural programmable accelerators 结构可编程加速器的CoDe-X分区性能分析
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584593
R. Hartenstein, J. Becker
{"title":"Performance analysis in CoDe-X partitioning for structural programmable accelerators","authors":"R. Hartenstein, J. Becker","doi":"10.1109/HSC.1997.584593","DOIUrl":"https://doi.org/10.1109/HSC.1997.584593","url":null,"abstract":"Presents the performance analysis process within the parallelizing compilation environment CoDe-X (CoDesign of Xputers) for simultaneous programming of transputer-based accelerators and their hosts. This paper briefly introduces its hardware/software co-design strategies at two levels of partitioning. CoDe-X performs, at the first level, a profiling-driven host/accelerator partitioning for performance optimization and, at the second level, a resource-driven sequential/structural partitioning of the accelerator source code in order to optimize the utilization of its reconfigurable resources. The analysis of candidate (task) performances in CoDe-X has to be done for both a procedural (sequential) programmable host processor and a structural programmable data-driven accelerator processor. In complete application time estimation, data dependencies for parallel task execution (hosts/accelerators) are considered. To stress the significance of this application development methodology, this paper gives an introduction to the target hardware platform.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125841784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Critical path driven cosynthesis for heterogeneous target architectures 关键路径驱动的异构目标体系结构协同合成
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584573
P. Bjørn-Jørgensen, J. Madsen
{"title":"Critical path driven cosynthesis for heterogeneous target architectures","authors":"P. Bjørn-Jørgensen, J. Madsen","doi":"10.1109/HSC.1997.584573","DOIUrl":"https://doi.org/10.1109/HSC.1997.584573","url":null,"abstract":"This paper presents a critical path driven algorithm to produce a static schedule of a single-rate system onto a heterogeneous target architecture. Our algorithm is a list based scheduling algorithm which concurrently assigns tasks to processors and allocates nets to interprocessor communication. Experimental results show that our algorithm is able to find good results, as compared to other methods, in small amount of CPU time.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123946111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 61
Run-time scheduler synthesis for hardware-software systems and application to robot control design 软硬件系统的运行调度程序综合及其在机器人控制设计中的应用
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584586
V. Mooney, T. Sakamoto, G. De Micheli
{"title":"Run-time scheduler synthesis for hardware-software systems and application to robot control design","authors":"V. Mooney, T. Sakamoto, G. De Micheli","doi":"10.1109/HSC.1997.584586","DOIUrl":"https://doi.org/10.1109/HSC.1997.584586","url":null,"abstract":"We present a tool that automatically generates a run-time scheduler for a target architecture from a heterogeneous system-level specification in both Verilog HDL and C. Part of the run-time scheduler is implemented in hardware, which allows the scheduler to be predictable in being able to meet hard real-time constraints, while part is implemented in software, thus supporting features typical of software schedulers. We describe the tool flow and target architecture, synthesis of the control portion of the run-time scheduler in hardware, and control of the software using interrupts. Finally, we conclude with a sample application of the tool to a robot design example.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121657279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
An approach to the synthesis of HW and SW in codesign 协同设计中硬件与软件的综合方法
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584599
V. Carchiolo, M. Malgeri, G. Mangioni
{"title":"An approach to the synthesis of HW and SW in codesign","authors":"V. Carchiolo, M. Malgeri, G. Mangioni","doi":"10.1109/HSC.1997.584599","DOIUrl":"https://doi.org/10.1109/HSC.1997.584599","url":null,"abstract":"The main aim of hardware/software (HW/SW) codesign is to be able to design a whole system without excessive preliminary constraints on the mapping or partitioning of the hardware and software parts. At present, given the availability of CAD tools and hardware devices, the sector which seems to offer most prospects of codesign methodology application is that of embedded systems. This paper presents a codesign approach based on the formal technique called TTL (Templated T-LOTOS, where T-LOTOS is a language which extends LOTOS by adding the capability to describe time explicitly). This paper shows how the synthesis of both the HW and SW modules described by TTL into RTL (register transfer level) or C languages, respectively, can be performed thanks to a semantic-based translation.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123495395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Trade-offs in the design of mixed hardware-software systems-a perspective from industry 混合软硬件系统设计中的权衡取舍——来自工业的视角
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584580
K. Vissers
{"title":"Trade-offs in the design of mixed hardware-software systems-a perspective from industry","authors":"K. Vissers","doi":"10.1109/HSC.1997.584580","DOIUrl":"https://doi.org/10.1109/HSC.1997.584580","url":null,"abstract":"Many systems in the field of consumer electronics devices and computers consist of a hardware platform and of software running on that platform. In the design of these systems many trade-offs have to be made. In the design of the hardware platform trade-offs have to be made between programmable components and dedicated components. The programming of the hardware platform also contains many trade-offs. Here a \"software architecture\" needs to be developed that spans several layers, using well defined interfaces, e.g. application programming interfaces (APIs). The software contains often device drivers, an operating system, and end-user applications. In embedded systems the end-user can often not program the system directly, e.g. one cannot program the look and feel or contents of the on-screen display of your TV. In practical situations system design is based on many constraints, and seldom starts from scratch. The hardware interface to the system can be given, the models of processors that can be used can be limited, and software interfaces can be required. The trade-offs are in the hardware platform design and in the software design.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116575196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Software architecture synthesis for retargetable real-time embedded systems 可重定向实时嵌入式系统的软件体系结构综合
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584587
P. Chou, G. Borriello
{"title":"Software architecture synthesis for retargetable real-time embedded systems","authors":"P. Chou, G. Borriello","doi":"10.1109/HSC.1997.584587","DOIUrl":"https://doi.org/10.1109/HSC.1997.584587","url":null,"abstract":"Retargetability of embedded system descriptions not only enables better exploration of the design space and evaluation of cost/performance tradeoffs but also enhances design maintainability and adaptivity to new technologies. Unfortunately, the traditional boundary between run-time support and user-code encourages use of ad hoc architecture-specific features that lack the structure to permit automatic code synthesis for the satisfaction of timing constraints. This work proposes a specification style for control dominated embedded systems that can be easily retargeted via automatic synthesis of the software architecture and run-time support. Unlike previous work, user-specified modes are an integral part of the run-time system and isolate architecture-specific details while scoping timing constraints to enable more efficient scheduling.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129419066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Enforcing schedulability of multi-task systems by hardware-software codesign 通过软硬件协同设计实现多任务系统的可调度性
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584571
Youngsoo Shin, Kiyoung Choi
{"title":"Enforcing schedulability of multi-task systems by hardware-software codesign","authors":"Youngsoo Shin, Kiyoung Choi","doi":"10.1109/HSC.1997.584571","DOIUrl":"https://doi.org/10.1109/HSC.1997.584571","url":null,"abstract":"This paper deals with the problem of hardware-software codesign of hard real-time systems. For a given task set, we perform an exact schedulability test to determine whether the task set is schedulable or not. When there is a task that cannot meet the deadline, we compute the amount of time by which the deadline is missed. Then we determine which tasks should reduce their execution time to compensate that amount of time deviation. The reduction of execution time is achieved by implementing parts of the tasks with hardware. With this approach, we can systematically design a hard real-time system which is infeasible with all software implementation. Preliminary experimental results are given to demonstrate the effectiveness of our approach.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130089485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A generic multi-unit architecture for codesign methodologies 用于协同设计方法的通用多单元体系结构
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584574
G. Gogniat, M. Auguin, C. Belleudy
{"title":"A generic multi-unit architecture for codesign methodologies","authors":"G. Gogniat, M. Auguin, C. Belleudy","doi":"10.1109/HSC.1997.584574","DOIUrl":"https://doi.org/10.1109/HSC.1997.584574","url":null,"abstract":"This paper introduces a template architecture for codesign methodologies. This architecture is based on a data synchronized control scheme that is well adapted to the implementation of numerous telecommunication applications specified, with a data flow model. The template architecture permits an easy integration of HW and SW coarse grain units. Communications between internal units are assumed to have an asynchronous protocol that is the more general transfer mechanism but also the more expensive in hardware resources. Hence, a communication synthesis method is presented that transforms asynchronous communications into synchronous ones. Results on an acoustic echo canceller illustrate the interest of the approach.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123170218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A codesign environment supporting hardware/software modeling at different levels of detail 支持不同细节层次的硬件/软件建模的协同设计环境
Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI: 10.1109/HSC.1997.584589
Sanjaya Kumar, F. Rose
{"title":"A codesign environment supporting hardware/software modeling at different levels of detail","authors":"Sanjaya Kumar, F. Rose","doi":"10.1109/HSC.1997.584589","DOIUrl":"https://doi.org/10.1109/HSC.1997.584589","url":null,"abstract":"Hybrid modeling is a technique that integrates performance and behavioral models within a common simulation. This approach allows behavioral components, containing mixtures of hardware and software, to be evaluated within the context of the system being developed. Hybrid interfaces are required to integrate the behavioral models with the performance models. This paper presents Honeywell's VHDL-based approach to codesign using hybrid modeling. The structure of the hybrid interface is described, and a hybrid interface for a processor model is presented. A four processor Myrinet example is provided to illustrate hardware/software modeling at different levels of detail. We are evaluating our methodology using an internal application.","PeriodicalId":104833,"journal":{"name":"Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124986082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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