An approach to the synthesis of HW and SW in codesign

Abstract

The main aim of hardware/software (HW/SW) codesign is to be able to design a whole system without excessive preliminary constraints on the mapping or partitioning of the hardware and software parts. At present, given the availability of CAD tools and hardware devices, the sector which seems to offer most prospects of codesign methodology application is that of embedded systems. This paper presents a codesign approach based on the formal technique called TTL (Templated T-LOTOS, where T-LOTOS is a language which extends LOTOS by adding the capability to describe time explicitly). This paper shows how the synthesis of both the HW and SW modules described by TTL into RTL (register transfer level) or C languages, respectively, can be performed thanks to a semantic-based translation.