Performance analysis in CoDe-X partitioning for structural programmable accelerators

Abstract

Presents the performance analysis process within the parallelizing compilation environment CoDe-X (CoDesign of Xputers) for simultaneous programming of transputer-based accelerators and their hosts. This paper briefly introduces its hardware/software co-design strategies at two levels of partitioning. CoDe-X performs, at the first level, a profiling-driven host/accelerator partitioning for performance optimization and, at the second level, a resource-driven sequential/structural partitioning of the accelerator source code in order to optimize the utilization of its reconfigurable resources. The analysis of candidate (task) performances in CoDe-X has to be done for both a procedural (sequential) programmable host processor and a structural programmable data-driven accelerator processor. In complete application time estimation, data dependencies for parallel task execution (hosts/accelerators) are considered. To stress the significance of this application development methodology, this paper gives an introduction to the target hardware platform.