一种通用可重构协处理器的硬件/软件协同设计方法

Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97 Pub Date : 1997-03-24 DOI:10.1109/HSC.1997.584594

S. Kimura, Y. Itou, M. Hirao, Katsumasa Watanabe, M. Yukishita, A. Nagoya

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引用次数: 9

摘要

给出了一个具有可重构协处理器的计算机系统的硬件/软件协同设计方法。可重构协处理器由fpga、内部缓存和控制部分组成，并与计算机系统的系统总线相连。本文给出了可重构协处理器的体系结构、硬件/软件分离方法和基于dma的内存共享协作方法。我们还展示了合作的例子，以及我们快速执行用户流程的方法的有效性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A hardware/software codesign method for a general purpose reconfigurable co-processor

Shows a hardware/software codesign method for a computer system with a reconfigurable co-processor. The reconfigurable co-processor is constructed from FPGAs, internal cache and a control part, and is connected to the system bus of the computer system. This paper shows the architecture of the reconfigurable co-processor, a hardware/software separation method and a co-operation method via DMA-based memory sharing. We also show co-operation examples and the effectiveness of our approach for the fast execution of user processes.

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Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97

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