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ESSDERC 2007 - 37th European Solid State Device Research Conference最新文献

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Analytical and compact modelling of the I-MOS (impact ionization MOS) I-MOS(冲击电离MOS)的分析与紧凑建模
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430935
F. Mayer, T. Poiroux, G. Le Carval, L. Clavelier, S. Deleonibus
{"title":"Analytical and compact modelling of the I-MOS (impact ionization MOS)","authors":"F. Mayer, T. Poiroux, G. Le Carval, L. Clavelier, S. Deleonibus","doi":"10.1109/ESSDERC.2007.4430935","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430935","url":null,"abstract":"The Impact Ionization MOSFET (I-MOS) is a potential candidate for the post-CMOS era, allowing very sharp subthreshold slopes, down to a few mV/dec. For the first time, an analytical model is developed for this new kind of device. In the first part, the analytical model is explained and compared with TCAD results. The second part deals with the compact modeling of the I-MOS, allowing simulations of inverters.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"89 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115984205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A reliable and accurate approach to assess NBTI behavior of state-of-the-art pMOSFETs with fast-WLR 一种可靠和准确的方法来评估最先进的pmosfet快速wlr的NBTI行为
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430896
C. Schlunder, R. Vollertsen, W. Gustin, H. Reisinger
{"title":"A reliable and accurate approach to assess NBTI behavior of state-of-the-art pMOSFETs with fast-WLR","authors":"C. Schlunder, R. Vollertsen, W. Gustin, H. Reisinger","doi":"10.1109/ESSDERC.2007.4430896","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430896","url":null,"abstract":"NBTI is a key challenge of today's technologies and could be assessed so far only by relative long stress durations. The On-the-fly characterization seems to be a proper method for fast-WLR, but shows also some problems. This work describes for the first time the application of OTF in combination with self-heating test structures and a method to correct the initial value without special equipment. Challenges and different solutions are introduced and discussed. We compare data from very fast non standard measurements with fWLR data acquired with regular test equipment. The insight we gained suggests that fWLR provides a suitable means for fast NBTI monitoring.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127373730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A novel base current phenomenon in SiGe HBTs operating in inverse mode 在反向模式下工作的SiGe HBTs中的一种新的基极电流现象
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430950
A. Appaswamy, J. Cressler, G. Niu
{"title":"A novel base current phenomenon in SiGe HBTs operating in inverse mode","authors":"A. Appaswamy, J. Cressler, G. Niu","doi":"10.1109/ESSDERC.2007.4430950","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430950","url":null,"abstract":"The inverse mode operation of SiGe HBTs down to cryogenic temperatures is examined for the first time. A novel base current \"flattening\" is observed at low temperatures, and the physics behind this unusual current-gain enhancing behavior is examined in detail using a combination of measurement and TCAD simulations.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127442326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Degradation of spectral response and dark current of CMOS image sensors in deep-submicron technology due to γ-irradiation γ辐照对深亚微米CMOS图像传感器光谱响应和暗电流的影响
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430955
P. R. Rao, Xinyang Wang, A. Theuwissen
{"title":"Degradation of spectral response and dark current of CMOS image sensors in deep-submicron technology due to γ-irradiation","authors":"P. R. Rao, Xinyang Wang, A. Theuwissen","doi":"10.1109/ESSDERC.2007.4430955","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430955","url":null,"abstract":"In this paper, a model for the spectral response of 4-T (4-Transistor) CMOS image sensors in deep-submicron technology is developed to study the sensor's sensitivity towards gamma-ray irradiation. It is found that the spectral degradation due to gamma-rays is mainly through changes in the top-layer material characteristics and Si/SiO2 interface. There is a non-trivial contribution of STI (shallow trench isolations) towards the dark current of the sensor, and it turns out to be highly sensitive to radiation damage.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132257458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Band edge NMOS work function for nickel fully-silicided (FUSI) gate obtained by the insertion of novel Y-, Tb-, and Yb-based interlayers 通过插入新型的Y、Tb和yb基中间层，获得了全硅化镍栅极的带边NMOS功函数
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430916
A. Lim, R.T.-P. Lee, Xin Peng Wang, W. Hwang, C. Tung, D. Lai, G. Samudra, D. Kwong, Y. Yeo
{"title":"Band edge NMOS work function for nickel fully-silicided (FUSI) gate obtained by the insertion of novel Y-, Tb-, and Yb-based interlayers","authors":"A. Lim, R.T.-P. Lee, Xin Peng Wang, W. Hwang, C. Tung, D. Lai, G. Samudra, D. Kwong, Y. Yeo","doi":"10.1109/ESSDERC.2007.4430916","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430916","url":null,"abstract":"Nickel fully-silicided (FUSI) gate work function Phin, was successfully tuned for the first time by the insertion of novel yttrium-(Y) based, terbium-(Tb) based, or ytterbium-(Yb) based interlayer at the gate/dielectric interface. Band edge Ni-FUSI gate Phim, (4.01 -4.11 eV) were obtained in a gate-first process flow (950 or 1000degC anneal) by an inserted ultra-thin (~1 nm) interlayer on SiO2 dielectric. We further demonstrate that gate-first implementation of the interlayers in a NiSi/HfO2 gate stack can realize a low Phim, of ~4.28 eV without dopant incorporation or Ni-alloying. In addition, NiSi Phim, modulation between Si midgap and band edge could be achieved by varying the interlayer thickness or M-silicide phase.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123309491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Theoretical analysis of XtreMOS™ power transistors XtreMOS™功率晶体管的理论分析
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430968
J. Roig, B. Desoete, P. Moens, M. Tack
{"title":"Theoretical analysis of XtreMOS™ power transistors","authors":"J. Roig, B. Desoete, P. Moens, M. Tack","doi":"10.1109/ESSDERC.2007.4430968","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430968","url":null,"abstract":"This work provides a new theoretical approach addressed to the XtreMOSTM and equivalent structures. An analytical sRonxBVdss model is provided to demonstrate the superior electrical performance of XtreMOSTM structure in the domain of the high power MOSFETs at medium voltage capability (50-200 V). Moreover, geometrical and technological parameters can be easily optimized by means of simple expressions. In order to support and validate the theoretical approach, numerical simulation and experimental data are included.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116105909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Embedded FLASH memory thermal budget impact on core CMOS 90nm devices 嵌入式闪存热预算对核心CMOS 90nm器件的影响
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430928
J. Carrere, F. Larman, E. van der Vegt, M. Bocat, N. Auriac, N. Cherault, M. Charleux, K. Rochereau, M. Hopstaken, R. Pantel, D. Boter, D. Dormans
{"title":"Embedded FLASH memory thermal budget impact on core CMOS 90nm devices","authors":"J. Carrere, F. Larman, E. van der Vegt, M. Bocat, N. Auriac, N. Cherault, M. Charleux, K. Rochereau, M. Hopstaken, R. Pantel, D. Boter, D. Dormans","doi":"10.1109/ESSDERC.2007.4430928","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430928","url":null,"abstract":"In an embedded FLASH 90 nm technology, core devices behavior is modified by the thermal budget needed to process the specific FLASH dielectrics. When these steps are performed after the logic poly deposition, we observe two main kinds of changes: first the substrate doping is modified due to diffusion and segregation effects. Then, the poly morphology changes, this leads to larger poly grain size and gate doping change. To limit these effects and maintain the full compatibility with CMOS logic, thermal budget limitations are finally presented.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125365366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Negative bias temperature instability: Recoverable versus permanent degradation 负偏置温度不稳定性:可恢复与永久退化
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430895
Tibor Grasser, B. Kaczer
{"title":"Negative bias temperature instability: Recoverable versus permanent degradation","authors":"Tibor Grasser, B. Kaczer","doi":"10.1109/ESSDERC.2007.4430895","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430895","url":null,"abstract":"The analysis of negative bias temperature instability (NBTI) conventionally focuses on the stress phase where features like the power-law exponent, the temperature-dependence, and saturation of the observed threshold voltage shift have been extensively studied. As soon as the stress is removed, however, relaxation sets in, restoring at least some of the degradation. Although some studies on the relaxation phase have been presented, few authors have acknowledged the importance of the relaxation phase as a means of deepening our understanding of NBTI. We present a detailed analysis of NBTI relaxation, show that even at lower stressing voltages a permanent/slowly relaxing component is present, and demonstrate how this initially less dominant component might eventually determine the device lifetime.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125723983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
The ESBT® (Emitter-Switched Bipolar Transistor): a new monolithic power actuator technology devoted to high voltage and high frequency applications ESBT®(发射开关双极晶体管):一种新的单片功率致动器技术，专门用于高压和高频应用
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430967
V. Enea, D. Kroell, M. Messina, C. Ronsisvalle
{"title":"The ESBT® (Emitter-Switched Bipolar Transistor): a new monolithic power actuator technology devoted to high voltage and high frequency applications","authors":"V. Enea, D. Kroell, M. Messina, C. Ronsisvalle","doi":"10.1109/ESSDERC.2007.4430967","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430967","url":null,"abstract":"A novel power actuator having a good switching behaviour along with a highly performing on-state conduction characteristic is presented. The device is a monolithic integration of a high voltage bipolar transistor and a low voltage MOSFET connected in cascode configuration. The sandwich structure so obtained has shown very attractive electrical performance and ruggedness. This paper also demonstrates how this new structure can be easily tailored according to the application requirements. Finally a comparison with other power actuator such as a high voltage power MOSFET and a fast IGBT proves its superiority in terms of energy losses especially at high working frequencies.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124581633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Strain enhancement in spacerless N-channel FinFETs with silicon-carbon source and drain stressors 采用硅碳源和漏极应力源的无间隔n沟道finfet的应变增强
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430901
T. Liow, K. Tan, R.T.-P. Lee, M. Zhu, K. Hoe, G. Samudra, N. Balasubramanian, Y. Yeo
{"title":"Strain enhancement in spacerless N-channel FinFETs with silicon-carbon source and drain stressors","authors":"T. Liow, K. Tan, R.T.-P. Lee, M. Zhu, K. Hoe, G. Samudra, N. Balasubramanian, Y. Yeo","doi":"10.1109/ESSDERC.2007.4430901","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430901","url":null,"abstract":"By removing the SiN gate spacers in n-channel FinFETs with Silicon-Carbon (SiC) Source and Drain (S/D) stressors, the mechanical stress equilibrium is perturbed. Higher tensile channel stress can be achieved, after the transistor structure attains mechanical equilibrium once again after spacer removal. This stress increase results in up to ~15 % further IDsat enhancement over strained SiC S/D FinFETs with spacers intact. Peak Gm is enhanced by ~33 %.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"107 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131372229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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