嵌入式闪存热预算对核心CMOS 90nm器件的影响

J. Carrere, F. Larman, E. van der Vegt, M. Bocat, N. Auriac, N. Cherault, M. Charleux, K. Rochereau, M. Hopstaken, R. Pantel, D. Boter, D. Dormans
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引用次数: 2

摘要

在嵌入式FLASH 90纳米技术中,处理特定FLASH电介质所需的热预算可以改变核心器件的行为。当这些步骤在逻辑聚沉积后进行时,我们观察到两种主要的变化:首先,由于扩散和偏析效应,衬底掺杂被修饰。然后,多晶形貌发生变化,导致多晶尺寸增大,栅极掺杂发生变化。为了限制这些影响并保持与CMOS逻辑的完全兼容性,最后提出了热预算限制。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Embedded FLASH memory thermal budget impact on core CMOS 90nm devices
In an embedded FLASH 90 nm technology, core devices behavior is modified by the thermal budget needed to process the specific FLASH dielectrics. When these steps are performed after the logic poly deposition, we observe two main kinds of changes: first the substrate doping is modified due to diffusion and segregation effects. Then, the poly morphology changes, this leads to larger poly grain size and gate doping change. To limit these effects and maintain the full compatibility with CMOS logic, thermal budget limitations are finally presented.
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