2010 NASA/ESA Conference on Adaptive Hardware and Systems最新文献_第4页

A fault-tolerant system-on-programmable-chip based on domain-partition and blind reconfiguration 基于域划分和盲重构的可编程芯片容错系统

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546245

L. Shang, Mi Zhou, Yu Hu

{"title":"A fault-tolerant system-on-programmable-chip based on domain-partition and blind reconfiguration","authors":"L. Shang, Mi Zhou, Yu Hu","doi":"10.1109/AHS.2010.5546245","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546245","url":null,"abstract":"Field programmable gate arrays (FPGAs) are widely used in building Systems-on-Programmable-Chips (SOPCs) since they contain plenty of reconfigurable heterogeneous resources providing the facility to implement various intellectual property cores. However, with the shrinking device feature size and the increasing die area, nowadays FPGAs can be deeply affected by the errors induced by electromigration and radiation, which results in challenges of building reliable SOPCs. In this paper, a SOPC implementing a smart 1553B bus node is presented to investigate the challenges and illustrate a feasible approach for building a complex system aimed at high reliability and low recovery latency on a commercial FPGA. First, a general reliability model, the DomainPartition (DP) model, is introduced to formulate the SOPCs which contain multiple alternative configurations proving the fault recovery capability. The assignment of the alternative configurations for maximizing the reliability is then determined according to a first-order optimal solution under the DP framework. Finally, the blind reconfiguration technique is used to reduce the recovery latency. The experiments based on a Monte Carlo simulation approach are carried out to evaluate the reliability and the latency. The obtained results show that higher reliability is attainable with less overhead than the generic triple-modular redundancy method.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122541172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

HTPCP: GNSS-R multi-channel cross-correlation waveforms post-processing solution for GOLD-RTR instrument HTPCP: GOLD-RTR仪器GNSS-R多通道互相关波形后处理方案

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546267

Guo Yi, David Atienza Alonso, A. Rius, S. Ribo, C. Ferrer

{"title":"HTPCP: GNSS-R multi-channel cross-correlation waveforms post-processing solution for GOLD-RTR instrument","authors":"Guo Yi, David Atienza Alonso, A. Rius, S. Ribo, C. Ferrer","doi":"10.1109/AHS.2010.5546267","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546267","url":null,"abstract":"Global navigation satellite system reflectometry (GNSS-R) remote sensing is a new remote sensing technique of satellite navigation application. Essentially, it entails a method of remote sensing that receives and processes microwave signals reflected from various surfaces. The GPS open-loop differential real-time receiver (GOLD-RTR) instrument have been proposed as GNSS-R instrument, to gather global positioning satellite system signals after they have been reflected from suitable surfaces (e.g. sea, ice and ground); and extract useful information about those surfaces. However to fully benefit from real-time characteristic, the overhead between the stringent real-time parallel processing and the storage of amount of multi-channel cross-correlation waveforms(CC-WAVs) prior to downlink issues have been addressed. Over last years, several embedded solutions for parallel processing are ready available: Symmetric Multiprocessing (SMP), Network-On-Chip (NOC). Indeed, higher performance is achieved, but bus congestion and memory allocation issues have increased with these new embedded solutions. This paper presents a novel architecture, namely, the Heterogeneous Transmission and Parallel Computing Platform (HTPCP); And the mandates imposed by the stringent timing constraints by a Dual-Port RAM (DPRAM). The pros and cons of different approaches are discussed, range from providing parallel computing to analyzing bus busy ratio and memory access time. The numerical results show that HTPCP reaches a speed-up of 8.17x in comparison to the SMP architecture, which enables the highest throughput in the real-time system design of GNSS-R.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131287180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An emerging adaptive architecture and compilation techniques 新兴的自适应架构和编译技术

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546268

Yong-Kyu Jung

引用次数: 0

Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study 一种自愈异步电路的可靠性估计与实验结果:个案研究

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546277

T. Panhofer, W. Friesenbichler, A. Steininger

引用次数: 1

Enabling technologies for self-aware adaptive systems 自我意识适应系统的使能技术

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546266

M. Santambrogio, H. Hoffmann, J. Eastep, A. Agarwal

{"title":"Enabling technologies for self-aware adaptive systems","authors":"M. Santambrogio, H. Hoffmann, J. Eastep, A. Agarwal","doi":"10.1109/AHS.2010.5546266","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546266","url":null,"abstract":"Self-aware computer systems will be capable of adapting their behavior and resources thousands of times a second to automatically find the best way to accomplish a given goal despite changing environmental conditions and demands. Such a capability benefits a broad spectrum of computer systems from embedded systems to supercomputers and is particularly useful for meeting power, performance, and resource-metering challenges in mobile computing, cloud computing, multicore computing, adaptive and dynamic compilation environments, and parallel operating systems. Some of the challenges in implementing self-aware systems are a) knowing within the system what the goals of applications are and if they are meeting them, b) deciding what actions to take to help applications meet their goals, and c) developing standard techniques that generalize and can be applied to a broad range of self-aware systems. This work presents our vision for self-aware adaptive systems and proposes enabling technologies to address these three challenges. We describe a framework called Application Heartbeats that provides a general, standardized way for applications to monitor their performance and make that information available to external observers. Then, through a study of a self-optimizing synchronization library called Smartlocks, we demonstrate a powerful technique that systems can use to determine which optimization actions to take. We show that Heartbeats can be applied naturally in the context of reinforcement learning optimization strategies as a reward signal and that, using such a strategy, Smartlocks are able to significantly improve performance of applications on an important emerging class of multicore systems called asymmetric multicores.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131510509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 43

Bio-inspired bit slice processors with self-test and self-repair mechanisms 具有自我测试和自我修复机制的仿生位片处理器

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546230

A. Stauffer, J. Rossier

引用次数: 0

A high-throughput, adaptive FFT architecture for FPGA-based space-borne data processors 基于fpga的星载数据处理器的高吞吐量、自适应FFT架构

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546270

K. Nguyen, J. Zheng, Yutao He, B. Shah

{"title":"A high-throughput, adaptive FFT architecture for FPGA-based space-borne data processors","authors":"K. Nguyen, J. Zheng, Yutao He, B. Shah","doi":"10.1109/AHS.2010.5546270","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546270","url":null,"abstract":"Historically, computationally-intensive data processing for space-borne instruments has heavily relied on ground-based computing resources. But with recent advances in functional densities of Field-Programmable Gate-Arrays (FPGAs), there has been an increasing desire to shift more processing on-board; therefore relaxing the downlink data bandwidth requirements. Fast Fourier Transforms (FFTs) are commonly-used building blocks for data processing applications, with a growing need to increase the FFT block size. Many existing FFT architectures have mainly emphasized on low power consumption or resource usage; but as the block size of the FFT grows, the throughput is often compromised first. In addition to power and resource constraints, space-borne digital systems are also limited to a small set of space-qualified memory elements, which typically lag behind the commercially available counterparts in capacity and bandwidth. The bandwidth limitation of the external memory creates a bottleneck for a large, high-throughput FFT design with large block size. In this paper, we present the Multi-Pass Wide Kernel FFT (MPWK-FFT) architecture for a moderately large block size (32K) with considerations to power consumption and resource usage, as well as throughput. We will also show that the architecture can be easily adapted for different FFT block sizes with different throughput and power requirements. The result is completely contained within an FPGA without relying on external memories. Implementation results are summarized.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123875269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths 可重构流水线数据路径的低开销软错误检测和校正方案

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546228

Sohan Purohit, S. R. Chalamalasetti, M. Margala

{"title":"Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths","authors":"Sohan Purohit, S. R. Chalamalasetti, M. Margala","doi":"10.1109/AHS.2010.5546228","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546228","url":null,"abstract":"In this paper, we describe a novel scheme for radiation hardening of high performance pipelined architectures and data paths. The proposed technique uses a local ground bus decoupled from the global ground using an additional pull down device, to detect a transient error. Combining the detector output with duplicated pipeline registers enables an instruction execution through the data path to be repeated as soon as the error is detected. The detector outputs from various stages in a pipelined data path are manipulated to maintain correctness of data in the event of a transient error detection and corresponding instruction roll back. The proposed technique is extremely effective for errors of different pulse widths and comes without the extra cost of error checking codes, watch dog processors and logic core duplication as used by other techniques in literature. Our scheme provides 100% radiation hardening over all process corners with only 9.7% and 21.73% area and power overhead respectively with the delay overhead being masked out by the pipeline stages used in modern high performance data path architectures.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116380298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

SDVMR – managing heterogeneity in space and time on multicore SoCs 管理多核soc在空间和时间上的异构性

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546269

Andreas F. Hofmann, K. Waldschmidt, Jan Haase

引用次数: 3

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546234

H J Kadim

引用次数: 0