An emerging adaptive architecture and compilation techniques

Abstract

An emerging adaptive front-end microprocessor architecture with associated compilation techniques for adaptive processor systems is introduced. The adaptive front-end architecture is capable of dealing with heterogeneous instruction sets for the integrated back-end microprocessor(s). The adaptive compilation techniques compile software codes of the back-end processor(s) and produce compatible and ciphered codes for the adaptive processor to enhance energy consumption, software security, performance, and underlying hardware resource utilization. The proposed adaptive processor scheme achieves 11% of branch elimination, 64% of instruction cache power conservation, and 29% of instruction packing without instruction memory overhead with the Michigan Benchmark (MiBench) for ARM 32-bit ISA.