2010 NASA/ESA Conference on Adaptive Hardware and Systems最新文献

Automated synthesis of 8-output voltage distributor using incremental, evolution 自动合成8输出电压分配器使用增量，进化

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546263

Y. Sapargaliyev, T. Kalganova

引用次数: 2

Evolutionary design and optimization of Wavelet Transforms for image compression in embedded systems 嵌入式系统图像压缩小波变换的演化设计与优化

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546265

R. Salvador, F. Moreno, T. Riesgo, L. Sekanina

引用次数: 9

Process reliability based trojans through NBTI and HCI effects 通过NBTI和HCI效应处理基于可靠性的木马

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546257

Y. Shiyanovskii, F. Wolff, Aravind Rajendran, C. Papachristou, D. Weyer, W. Clay

{"title":"Process reliability based trojans through NBTI and HCI effects","authors":"Y. Shiyanovskii, F. Wolff, Aravind Rajendran, C. Papachristou, D. Weyer, W. Clay","doi":"10.1109/AHS.2010.5546257","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546257","url":null,"abstract":"In this paper, we introduce the notion of process reliability based trojans which reduce the reliability of integrated circuits through malicious alterations of the manufacturing process conditions. In contrast to hardware/software trojans which either alter the circuitry or functionality of the IC respectively, the process reliability trojans appear as a result of alterations in the fabrication process steps. The reduction in reliability is caused by acceleration of the wearing out mechanisms for CMOS transistors, such as Negative Bias Temperature Instability (NBTI) or Hot Carrier Injection (HCI). The minor manufacturing process changes can result in creation of infected ICs with a much shorter lifetime that are difficult to detect. Such infected ICs fail prematurely and might lead to catastrophic consequences. The paper describes possible process alterations for both NBTI and HCI mechanisms that might result in creation of process reliability trojans. The paper also explores some possible detection techniques that can help identify the hidden trojans and discusses the various scenarios when process reliability based trojans lead to severe damages.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124076308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 87

Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems 高通量自适应信号处理系统的性能和面积效率转置存储器结构

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546272

Mohamed El-Hadedy, Sohan Purohit, M. Margala, S. J. Knapskog

引用次数: 7

Recovery method for a turn-off failure mode of a laser array on an ORGA ORGA上激光阵列关断失效模式的恢复方法

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546252

D. Seto, Minoru Watanabe

引用次数: 5

A formal model for specification and optimization of flexible communication systems 柔性通信系统规范与优化的形式化模型

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546253

Jiong Ou, Muhammad Farooq, Jan Haase, C. Grimm

引用次数: 2

Vision based navigation for autonomous space exploration 基于视觉的自主空间探索导航

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546273

G. Flandin, B. Polle, J. Lheritier, P. Vidal

引用次数: 8

FPGA implementation of an efficient high-throughput sphere decoder for MIMO systems based on the smallest singular value threshold 基于最小奇异值阈值的MIMO系统高效高吞吐量球体解码器的FPGA实现

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546236

Xiang Wu, J. Thompson

引用次数: 4

Reconfigurable machine vision systems using FPGAs 使用fpga的可重构机器视觉系统

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546238

C. Villalpando, R. Some

{"title":"Reconfigurable machine vision systems using FPGAs","authors":"C. Villalpando, R. Some","doi":"10.1109/AHS.2010.5546238","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546238","url":null,"abstract":"FPGAs provide a flexible architecture for implementing many different types of machine vision algorithms. They allow heavily parallel portions of those algorithms to be accelerated and optimized for high specific performance (MIPS:Watt ratio). In comparison to ASICS, FPGAs enable low cost, quick turn prototyping and algorithm development as well as lower production costs for small quantity and one off applications. FPGAs also have the ability to be reprogrammed in flight, allowing them to be configured for different applications as mission needs evolve. JPL has developed a suite of machine vision IP cores to accelerate many common machine vision tasks used in robotic mobility applications. Modules such as stereo correlation for ranging, filtering, optical flow, area based correlation, feature detection, and image homography and rectification allow the real-time processing of image data using much smaller systems with much less power draw then an appropriately sized general purpose processor. These modules, along with a vision processing framework, are being re-cast in a generic plug and play form to allow rapid, low cost configuration, reconfiguration, evolution and adaptation of next generation machine vision systems for mobile robotics.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126869187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Calibrating a predictive cache emulator for SoC design 为SoC设计校准预测缓存仿真器

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546246

S. Mancini, L. Pierrefeu, Zahir Larabi, Y. Mathieu

{"title":"Calibrating a predictive cache emulator for SoC design","authors":"S. Mancini, L. Pierrefeu, Zahir Larabi, Y. Mathieu","doi":"10.1109/AHS.2010.5546246","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546246","url":null,"abstract":"Pre-fetching in a memory hierarchy is known to alleviate the “memory wall” paradigm but its use is impeded because of the difficulty to estimate efficiency when used in a complex system such as a SoC (System on Chip) or NoC (Network on Chip). Therefore, some methods are needed to evaluate the benefit of pre-fetching at the earliest possible stage in a design flow to help the designer choose architectural parameters or transform the application algorithm. In this paper we show that the emulation platform implementing the nD-AP Cache (n-Dimensional Adaptive and Predictive Cache) allows to perform a platform-independent measurement of this cache efficiency. The nD-AP Cache performs pre-fetching in multidimensional arrays which are commonly used in image processing and multimedia applications. The obtained metric can be used to extrapolate the cache performance in a much broader system configuration. The method to compute this metric is the calibration process. The performed benchmarks show that the calibration process is confident. Also, we measured that the nD-AP Cache is two times faster than a standard PowerPC 2-way set associative cache in the context of an image processing kernel.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132538710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3